Hardware virtualization for media processing

• US 9,189,267 B2
• Filed: 11/17/2014
• Issued: 11/17/2015
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Kardashov, Timor, Kovalenko, Maxim, Elias, Arie, Ray, Guy
• Primary Examiner(s): Wu, Qing
• Application Number:
  US14/543,007
• Publication Number:
  US 20150074310A1
• Time in Patent Office: 365 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.

Claims

1. A method for processing media packets, comprising:

receiving a stream of media packets at a packet processor having a single CPU;

dividing processing operations for processing a received media packet into two or more frames of protected processing operations, wherein an elapsed time for processing the two or more frames of protected processing operations is less than a time interval between the receipt of media packets in the stream and respective frames of protected processing operations are temporally separated;

in the time interval between the receipt of media packets in the stream, alternating between (i) performing at the CPU the respective frames of protected processing operations in a protected processing environment that is not affected by other processing operations, and (ii) freeing up the CPU to selectively perform other processing operations in a non-protected processing environment during the temporal separation between the frames of protected processing operations.

2. The method for processing media packets according to claim 1, further comprising:

transitioning from the non-protected processing environment to the protected processing environment in response to an interrupt; and

generating the interrupt according to an interrupt interval that is less than the time interval, wherein the interrupt interval is dynamically adjusted based on quality of service requirements of the media packets.

3. The method for processing media packets according to claim 1, wherein the protected processing environment processes the received media packets in real-time.

4. The method for processing media packets according to claim 1, further comprising:

generating a stream of non-maskable, high-priority interrupts while in the non-protected environment in order to cause the CPU to switch to the protected processing environment.

5. The method for processing media packets according to claim 4, wherein generating each of the high-priority interrupt includes storing operating states of the CPU such that CPU operating states of the non-protected environment are preserved while the CPU is operating in the protected processing environment.

6. The method for processing media packets according to claim 4, further comprising operating the CPU so as to process voice over internet protocol (VoIP) media during the protected processing environment.

7. A media packet processor, comprising:

a single processing core that is configured to receive a stream of media packets; and

a central processing unit (CPU) that is configured to divide processing operations for processing a received media packet into two or more frames of protected processing operations, wherein an elapsed time for processing the two or more frames of protected processing operations is less than a time interval between the receipt of media packets in the stream and respective frames of protected processing operations are temporally separated,

wherein, in the time interval between the receipt of media packets in the stream, the CPU is configured to alternate between (i) performing at the CPU the respective frames of protected processing operations in a protected processing environment that is not affected by other processing operations, and (ii) selectively performing other processing operations in a non-protected processing environment during the temporal separation between the frames of the protected processing operation.

8. The media packet processor of claim 7, further comprising interrupt control circuitry configured to generate non-maskable, high-priority interrupts that cause the CPU to switch from the protected processing environment to the non-protected processing environment.

9. The media packet processor of claim 8, wherein during the protected processing environment the CPU is programmed to support voice over internet protocol (VoIP) media processing.

10. The media packet processor of claim 9, wherein at least one of a duration and frequency of the two or more frames of protected processing operations is dynamically adjustable to account for quality of service (QoS) requirements of the media packets.

11. The media packet processor of claim 7, further comprising a first state storage memory that stores operating states of the CPU upon activation of a high-priority interrupt, such that CPU operating states of the protected processing environment are preserved while the CPU is operating in the non-protected processing environment.

12. The media packet processor of claim 11, further comprising a second state storage memory that stores CPU operating states of the non-protected processing environment while the CPU is operating in the protected processing environment.

13. The media packet processor of claim 7, further comprising a timer circuit configured to periodically trigger high-priority interrupts at intervals less than the time interval of media packets received by the single processing core, and the other processing operations are configured to process media packets over multiple time slots in a manner that reduces latency of at least one application running on the CPU.

14. The media packet processor according to claim 7, wherein the protected processing environment processes the received media packets in real-time.