Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level

• US 9,189,329 B1
• Filed: 10/09/2012
• Issued: 11/17/2015
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Zhu, Jun, Cao, Joseph Jun, Lu, Sheng, Sutardja, Pantas
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US13/648,207
• Time in Patent Office: 1,134 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

A memory controller provides error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to identify an ECC protection level from a plurality of ECC protection levels for data that is to be stored in the memory device, generate ECC data for the data that is to be stored in the memory device using an ECC corresponding to the identified ECC protection level, store the generated ECC data in the cache, and store the data in the memory device.

Claims

1. An apparatus, comprising:

a cache configured to store error correcting code (ECC) data; and

a controller coupled to the cache, the controller configured to;

identify an ECC protection level from a plurality of ECC protection levels for a block of data that is to be stored in a memory device,

generate ECC data for the block of data that is to be stored in the memory device using an ECC corresponding to the identified ECC protection level,

store the generated ECC data in the cache as a portion of an ECC word, the ECC word including another portion that stores ECC data generated for a different block of data,

store the block of data in the memory device, and

store the ECC word in the memory device when the ECC word is a complete data word associated with the memory device.

2. The apparatus of claim 1, wherein the controller is configured to identify the ECC protection level based on (i) a location of the memory device where the block of data is to be stored, (ii) a type of the block of data that is to be stored in the memory device, or (iii) an operating condition of the memory device.

3. The apparatus of claim 2, wherein the controller is configured to identify the ECC protection level based on the operating condition of the memory device, and the operating condition of the memory device comprises a clock frequency used to operate the memory device.

4. The apparatus of claim 1, wherein the plurality of ECC protection levels are associated with a plurality of ECCs that are applied to data in a plurality of data lengths.

5. The apparatus of claim 1, wherein the plurality of ECC protection levels are associated with a plurality of ECCs that generate ECC data having a plurality of data lengths.

6. The apparatus of claim 1, wherein the controller is further configured to:

generate one or more addresses associated with one or more locations of the memory device where the generated ECC data is stored,

determine that the one or more addresses are associated with the generated ECC data stored in the cache, and

use the generated ECC data stored in the cache to detect or correct one or more errors in the block of data stored in the memory device.

7. A system, comprising:

a memory device; and

a controller configured to;

determine that a level of error correcting code (ECC) protection to be applied to data stored in the memory device is to be switched from a first ECC protection level to a second ECC protection level,

modify allocation of a portion of the memory device to redistribute the portion between an application data region that stores application data and an ECC data region that stores ECC data,

generate ECC data for system data stored in the memory device using an ECC associated with the second ECC protection level,

store the ECC data in the ECC data region, and

switch from the first ECC protection level to the second ECC protection level,

wherein the controller configured to generate the ECC data for the system data stored in the memory device using the ECC associated with the second ECC protection level comprises the controller configured to;

read the system data from the memory device,

perform error correction on the system data using an ECC and ECC data associated with the first ECC protection level, and

generate ECC data for the corrected system data using the ECC associated with the second ECC protection level.

8. The system of claim 7, wherein:

the second ECC protection level provides stronger ECC protection of the system data than the first ECC protection level; and

the controller configured to modify allocation of the portion of the memory device comprises the controller configured to;

deallocate a portion of the application data region, and

allocate the deallocated portion to the ECC data region.

9. The system of claim 7, wherein:

the second ECC protection level provides weaker ECC protection of the system data than the first ECC protection level; and

the controller configured to modify allocation of the portion of the memory device comprises the controller configured to;

deallocate a portion of the ECC data region, and

allocate the deallocated portion to the application data region.

10. The system of claim 7, wherein the controller is configured to determine that the level of ECC protection to be applied to the data stored in the memory device is to be switched from the first ECC protection level to the second ECC protection level based on a change in a clock frequency used to operate the memory device.

11. The system of claim 7, wherein the first ECC protection level and the second ECC protection level are associated with different ECCs that are applied to data in different data lengths.

12. The system of claim 7, wherein the first ECC protection level and the second ECC protection level are associated with different ECCs that generate ECC data having different data lengths.

13. A method, comprising:

determining that a level of error correcting code (ECC) protection to be applied to data stored in the memory device is to be switched from a first ECC protection level to a second ECC protection level;

modifying allocation of a portion of the memory device to redistribute the portion between an application data region that stores application data and an ECC data region that stores ECC data;

generating ECC data for system data stored in the memory device using an ECC associated with the second ECC protection level;

storing the ECC data in the ECC data region; and

switching from the first ECC protection level to the second ECC protection level,

wherein generating the ECC data for the system data stored in the memory device using the ECC associated with the second ECC protection level comprises;

reading the system data from the memory device;

performing error correction on the system data using an ECC and ECC data associated with the first ECC protection level; and

generating ECC data for the corrected system data using the ECC associated with the second ECC protection level.

14. The method of claim 13, wherein:

the second ECC protection level provides stronger ECC protection of the system data than the first ECC protection level; and

modifying allocation of the portion of the memory device comprises;

deallocating a portion of the application data region, and

allocating the deallocated portion to the ECC data region.

15. The method of claim 13, wherein:

the second ECC protection level provides weaker ECC protection of the system data than the first ECC protection level; and

modifying allocation of the portion of the memory device comprises;

deallocating a portion of the ECC data region, and

allocating the deallocated portion to the application data region.

16. The method of claim 13, wherein determining that the level of ECC protection to be applied to the data stored in the memory device is to be switched from the first ECC protection level to the second ECC protection level is based on a change in a clock frequency used to operate the memory device.