Selective cache-to-cache lateral castouts

• US 9,189,403 B2
• Filed: 12/30/2009
• Issued: 11/17/2015
• Est. Priority Date: 12/30/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guthrie, Guy L., Starke, William J., Stuecheli, Jeffrey, Williams, Derek E., Puzak, Thomas R.
• Primary Examiner(s): Bansal, Gurtej
• Application Number:
  US12/650,018
• Publication Number:
  US 20110161589A1
• Time in Patent Office: 2,148 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/12 Replacement control

Abstract

A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

Claims

1. A data processing system, comprising:

an interconnect fabric;

a system memory coupled to the interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;

a cache array in the first lower level cache, wherein the cache array includes a congruence class including a plurality of cache lines;

a cache directory in the first lower level cache, wherein the cache directory includes;

a chronology vector indicating a chronological access order of the plurality of cache lines in the congruence class;

a plurality of confidence indicators each associated with a respective one of the plurality of cache lines in the congruence class;

wherein the first lower level cache sets the respective associated one of the plurality of confidence indicators to indicate a lateral castout (LCO) in response to the first processor core accessing the associated cache line while the associated cache line has a position in the chronological access order at least as recent as a predetermined position;

wherein the first lower level cache, responsive to a data request, selects a victim cache line to be castout from among the plurality of cache lines in the congruence class of the first lower level cache and decides, based upon the confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory;

wherein the first processing unit, responsive to the first lower level cache deciding to perform the LCO, issues a lateral castout (LCO) command on the interconnect fabric and removes the victim cache line from the first lower level cache; and

wherein the second lower level cache, responsive to the LCO command, holds the victim cache line.

2. The data processing system of claim 1, wherein the first and second lower level caches are victim caches.

3. The data processing system of claim 1, wherein said lateral castout command identifies the second lower level cache as the destination.

4. The data processing system of claim 1, wherein the first processing unit, responsive to a coherence response to the LCO command indicating success of the LCO command, transmits the victim cache line to the second lower level cache.

5. The data processing system of claim 1, wherein the first lower level cache further decides between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory based upon a coherence state associated with the victim cache line.

6. The data processing system of claim 1, wherein the predetermined position is a more recent position than least recently used (LRU).

7. The data processing system of claim 1, wherein the first lower level cache selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines in the second class.

8. The data processing system of claim 7, wherein the first lower level cache maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

9. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, wherein the processing unit is first processing unit among the plurality of processing units and the plurality of processing units further includes a second processing unit including a second processor core and associated second upper and lower level caches, the first processing unit comprising:

a first processor core and associated first upper and first lower level caches;

a cache array in the first lower level cache, wherein the cache array includes a congruence class including a plurality of cache lines;

a cache directory in the first lower level cache, wherein the cache directory includes;

a chronology vector indicating a chronological access order of the plurality of cache lines in the congruence class;

a plurality of confidence indicators each associated with a respective one of the plurality of cache lines in the congruence class;

wherein the first lower level cache sets the respective associated one of the plurality of confidence indicators to indicate a lateral castout (LCO) in response to the first processor core accessing the associated cache line while the associated cache line has a position in the chronological access order at least as recent as a predetermined position;

wherein the first lower level cache, responsive to a data request, selects a victim cache line to be castout from among the plurality of cache lines in the congruence class of the first lower level cache and decides, based upon the confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory; and

wherein the first processing unit, responsive to the first lower level cache deciding to perform the LCO, issues a lateral castout (LCO) command on the interconnect fabric and removes the victim cache line from the first lower level cache, such that, responsive to the LCO command, the second lower level cache holds the victim cache line.

10. The processing unit of claim 9, wherein the first and second lower level caches are victim caches.

11. The processing unit of claim 9, wherein said lateral castout command identifies the second lower level cache as the destination.

12. The processing unit of claim 9, wherein the first processing unit, responsive to a coherence response to the LCO command indicating success of the LCO command, transmits the victim cache line to the second lower level cache.

13. The processing unit of claim 9, wherein the first lower level cache further decides between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory based upon a coherence state associated with the victim cache line.

14. The processing unit of claim 9, wherein the predetermined position is a more recent position than least recently used (LRU).

15. The processing unit of claim 9, wherein the first lower level cache selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines in the second class.

16. The processing unit of claim 15, wherein the first lower level cache maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.