EDRAM refresh in a high performance cache architecture

• US 9,189,415 B2
• Filed: 10/22/2012
• Issued: 11/17/2015
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fee, Michael, O'Neill, Arthur J. Jr., Sonnelitter, Robert J. III
• Primary Examiner(s): Savla, Arpan P.
• Application Number:
  US13/657,100
• Publication Number:
  US 20130046926A1
• Time in Patent Office: 1,121 Days
• Field of Search: 711/5, 711/105, 711/106, 711/118, 711/154, 365/185.22, 365/222
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Abstract

A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range.

Claims

1. A method for implementing cache memory refreshes in a high performance cache comprising:

receiving, by a cache controller, a memory refresh request, the memory refresh request being received from a memory refresh requestor and being a request to refresh contents of a memory address range in a cache memory, and receiving from a requestor a memory access request for the memory address range, and a pipeline mode of a cache pipeline;

storing the received pipeline mode in a mode register;

determining whether cache memory located at the memory address range is available or unavailable;

when the cache memory located at the memory address range is available, sending the memory access request for the memory address range to the memory request interpreter;

when the cache memory located at the memory address range is unavailable;

deferring the memory access request for the memory address range;

modifying the pipeline mode in the mode register to indicate the deferred memory access request for the memory address range; and

based on the pipeline mode being modified, attempting the memory access request by a subsequent request from the requestor;

receiving the memory refresh request and the memory access request by the memory request interpreter from the cache controller, the memory request interpreter giving higher priority to the memory refresh request than a priority given to the memory access request; and

based on receiving the memory refresh request, refreshing data in the memory address range.

2. The method of claim 1, wherein the cache memory comprises embedded dynamic random access memory (eDRAM).

3. The method of claim 1, wherein the memory access request received by the cache controller further comprises:

an identification (ID), the ID indicating that the memory access request is not a refresh request; and

the memory address range.

4. The method of claim 1, wherein the cache memory degrades over a period of time, and the method further comprises the memory refresh requestor sending memory refresh requests at a refresh interval, the refresh interval comprising a number of processing cycles corresponding to a maximum number of processing cycles that can be processed over the period of time.

5. The method of claim 1, wherein the method further comprises the memory request interpreter receiving memory access requests from a plurality of memory access request sources.

6. The method of claim 1, wherein the cache memory is a level four cache.

7. The method of claim 1, wherein the memory address range targeted by the memory refresh request is maintained within the cache pipeline, and the memory address range is incremented in the cache pipeline based on receiving the memory refresh request.

8. The method of claim 1, further comprising placing the memory access request on the cache pipeline.

9. The method of claim 1, further comprising receiving, by the cache controller an additional signal from the requestor, wherein the pipeline mode is only modified by the cache controller based on the additional signal indicating that the cache controller is permitted to modify the pipeline mode.

10. The method of claim 1, wherein the requestor comprises a core of the computer system.

11. The method of claim 1, wherein the requestor comprises a cache of the computer system that is a lower-level cache than the cache that receives the memory access request from the requestor.