Data interleaving module

• US 9,189,440 B2
• Filed: 07/14/2014
• Issued: 11/17/2015
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pilolli, Luigi, Gallese, Maria-Luisa, Castelli, Mauro
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US14/330,076
• Publication Number:
  US 20150019787A1
• Time in Patent Office: 491 Days
• Field of Search: 365/230.02, 365/185.03, 365/185.11, 365/189.02, 365/189.16, 365/189.17
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 2212/254 Distributed memory
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Claims

1. An apparatus, comprising:

a register;

a plurality of modules coupled to the register; and

a bus coupled to the plurality of modules;

wherein the apparatus is configured to;

transfer amounts of the data corresponding to the selected one of the plurality of data densities to respective modules according to a selected one of a plurality of densities per memory cell; and

transfer the data from the respective modules to the register.

2. The apparatus of claim 1, wherein the apparatus is configured to interleave the data among the plurality of modules such that a unit of the data received from the bus is interleaved to only one of the plurality of modules.

3. The apparatus of claim 2, wherein the plurality of modules are configured to transfer the interleaved data to the register simultaneously.

4. The apparatus of claim 3, wherein the plurality of modules are each coupled to the register by a respective number of regions.

5. The apparatus of claim 4, wherein the number of regions comprises a number of regions greater than one, and wherein each of the plurality of modules is configured to transfer the interleaved data to the register in parallel by the respective number of regions.

6. The apparatus of claim 5, wherein each of the plurality of modules is configured to transfer one byte of the interleaved data per region per data cycle.

7. The apparatus of claim 6, wherein the apparatus is configured to output data from a particular memory cell with a configurable data quantization.

8. The apparatus of claim 7, wherein the apparatus is configured to program a plurality of memory cells with a configurable data density per memory cell.

9. An apparatus, comprising:

a bus coupled to a plurality of modules;

a register including a plurality of portions corresponding to the plurality of modules, wherein the register is coupled to the bus by the plurality of modules;

wherein each of the plurality of modules is configured to receive data from a respective one of the plurality of portions of the register; and

wherein the apparatus is configured to transfer the data from each of the plurality of modules to the bus such that an amount of data corresponding to the selected data density is output from each of the plurality of modules.

10. The apparatus of claim 9, wherein each of the plurality of modules includes sensing circuitry and wherein each of the plurality of modules is configured to sense the data from the respective one of the plurality of portions of the register.

11. The apparatus of claim 9, wherein the apparatus is configured to selectively enable the plurality of modules to transition from data placer mode to threshold voltage (Vt) placer mode.

12. The apparatus of claim 9, wherein the apparatus is configured to receive a signal indicating the selected one of the plurality of configured data densities per memory cell.

13. An apparatus, comprising:

a module controller coupled to;

a data scrambler to provide a connection to a bus; and

a number of regions to provide a connection to a register;

wherein the module controller is configured to;

cause the data scrambler to interleave amounts of data from the bus according to a selected data density; and

transfer the interleaved data via the plurality of regions.

14. The apparatus of claim 13, wherein the number of regions correspond 1:

1 to a number of bytes of data that can be transferred in parallel.

15. The apparatus of claim 14, wherein the data scrambler is coupled to the number of regions via a data line driver, and wherein the module controller is configured to cause the data scrambler to send the interleaved data to a data line driver.

16. The apparatus of claim 15, wherein the module controller is configured to cause the data line driver to transfer respective portions of the interleaved data via each of the number of regions.

17. The apparatus of claim 14, wherein the module controller is configured to control different numbers of the number of regions according to different selected data densities.

18. The apparatus of claim 17, wherein the number of regions comprises four and wherein each region includes eight data lines.

19. The apparatus of claim 13, wherein the module controller is configured to receive a signal indicating the configured data density from the bus.

20. The apparatus of claim 13, wherein the module controller is configured to cause the data scrambler to transfer an amount of data corresponding to the selected data density to the bus during a plurality of clock cycles.