Generic data scrambler for memory circuit test engine

• US 9,190,173 B2
• Filed: 03/30/2012
• Issued: 11/17/2015
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kobla, Darshan, Zimmerman, David, Johnson, John C., Natarajan, Vimal K.
• Primary Examiner(s): McMahon, Daniel
• Application Number:
  US13/997,156
• Publication Number:
  US 20140013169A1
• Time in Patent Office: 1,327 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.

Claims

1. A stacked memory device comprising:

a memory stack including one or more memory die layers; and

a system element coupled with the memory stack, the system element including;

a memory controller for the memory stack,

a built-in self-test (BIST) circuit to test the memory stack, and

a generic data scrambler to scramble data for the testing of the memory stack, the scrambling of the data being performed according to a data scrambling algorithm for the memory stack, the data scrambling algorithm to provide mapping between logical locations and physical locations for data storage in the memory stack, the operation of the data scrambling algorithm being based at least in part on values of addresses for data, wherein the generic data scrambler includes;

a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, the programmable lookup table to generate a set of data factors based on addresses of the data for testing of the memory stack, and

a determination logic to combine the data for the testing of the memory stack with the data factors generated by the programmable lookup table to generate scrambled data;

wherein the BIST circuit and generic data scrambler are operable to implement multiple different data scrambling algorithms to support mappings between logical addresses and physical addresses for different memory types.

2. The stacked memory device of claim 1, wherein the lookup table includes a register file, values of the register file to be selected based on a value of at least a portion of bits of each of the addresses of the data for testing of the memory stack.

3. The stacked memory device of claim 2, wherein the programmable lookup table includes a multiplexer, the multiplexer to choose one of a plurality of sets of values of the register file based on one or more bits of each of the addresses of the data for testing of the memory stack.

4. The stacked memory device of claim 1, wherein the data scrambling algorithm is a function utilizing the addresses of data.

5. The stacked memory device of claim 1, wherein the system element is a system on chip (SoC).

6. The stacked memory device of claim 1, wherein the BIST circuit is to provide for testing after assembly of the stacked memory device including one or more of verifying operation of memory of the stacked memory device, and verifying connection of the memory to one or more logic components.

7. The stacked memory device of claim 1, wherein the BIST circuit is to provide for testing in operation of the stacked memory device.

8. The stacked memory device of claim 7, wherein the testing in operation of the stacked memory device includes a power on self-test of the stacked memory device.

22. The stacked memory device of claim 1, further comprising a tap input to load data factors for the data scrambling algorithm into the lookup table.

23. The stacked memory device of claim 1, wherein the determination logic includes multiple logic gates.

9. A method comprising:

pre-computing data factors for a data scrambling algorithm for a stacked memory device including a system element and a memory stack with one or more memory die layers, the data scrambling algorithm providing mapping between logical locations and physical locations for data storage in the memory stack;

loading the pre-computed data factors into a lookup table of a generic data scrambler of the stacked memory device, the lookup table to hold data factors for each possible outcome of the data scrambling algorithm;

receiving original data for testing of the memory stack of the stacked memory device and addresses for the original data;

determining a set of data factors for the testing of the memory stack from the lookup table based on the addresses for the original data; and

combining the original data for testing of the memory stack with the determined set of data factors from the lookup table to generate scrambled data according to the data scrambling algorithm.

10. The method of claim 9, further comprising performing a test of the stacked memory device using a BIST (built-in self-test) circuit of the stacked memory device, the test of the stacked memory device utilizing the scrambled data.

11. The method of claim 10, wherein performing the test of the stacked memory device includes testing after assembly of the stacked memory device, testing including one or more of verifying operation of memory of the stacked memory device, and verifying connection of the memory to one or more logic components.

12. The method of claim 10, wherein performing the test of the stacked memory device includes testing in operation of the stacked memory device in operation.

13. The method of claim 12, wherein testing in operation of the stacked memory device includes a power on self-test of the stacked memory device.

14. The method of claim 9, wherein combining the original data with the determined set of data factors includes XOR (exclusive OR) operations of the original data with the set of data factors.

15. A system including:

a bus to connect elements of the system;

a processor coupled with the bus to process data for the system;

a transmitter to transmit data, a receiver to receive data, or both a transmitter to transmit data and a receiver to receive data;

an omnidirectional antenna for data transmission, data reception, or both; and

memory coupled to the bus to hold data for processing by the processor, the memory including a stacked memory device, the stacked memory device including;

a memory stack including one or more layers of DRAM (dynamic random access) memory,

a system element coupled with the memory stack, the system element including;

a memory controller for the memory stack,

a built-in self-test (BIST) circuit to test the memory stack, and

a generic data scrambler to scramble data for the testing of the memory stack, the scrambling of the data being performed according to a data scrambling algorithm for the memory stack, the data scrambling algorithm to provide mapping between logical locations and physical locations for data storage in the memory stack, the operation of the data scrambling algorithm being based at least in part on values of addresses for data, wherein the generic data scrambler includes;

a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, the lookup table to generate a set of data factors based on addresses of the data for testing of the memory stack, and

a determination logic to combine the data for the testing of the memory stack with the data factors generated by the programmable lookup table to generate scrambled data;

wherein the BIST circuit and generic data scrambler are operable to implement multiple different data scrambling algorithms to support mappings between logical addresses and physical addresses for different memory types.

16. The system of claim 15, wherein the lookup table includes a register file, values of the register file to be selected based on a value of at least a portion of bits of each of the addresses of the data for testing of the memory stack.

17. The system of claim 16, wherein the lookup table includes a multiplexer, the multiplexer to choose one of a plurality of sets of values of the register file based on one or more bits of each of the addresses of the data for testing of the memory stack.

18. The system of claim 15, wherein the system is a computing system.

19. The system of claim 18, wherein the computing system is a tablet computer.

24. The system of claim 15, wherein the stacked memory device further includes a tap input to load data factors for the data scrambling algorithm into the lookup table.

25. The system of claim 15, wherein the determination logic includes multiple logic gates.

20. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

pre-computing data factors for a data scrambling algorithm for a stacked memory device including a system element and a memory stack with one or more memory die layers, the data scrambling algorithm providing mapping between logical locations and physical locations for data storage in the memory stack;

loading the pre-computed data factors into a lookup table of a generic data scrambler of the stacked memory device, the lookup table to hold data factors for each possible outcome of the data scrambling algorithm;

receiving original data for testing of the memory stack of the stacked memory device and addresses for the original data;

determining a set of lookup values for the testing of the memory stack from the lookup table based on the addresses for the original data; and

combining the original data for testing of the memory stack with the determined set of data factors from the lookup table to generate scrambled data according to the data scrambling algorithm.

21. The medium of claim 20, further comprising instructions that, when executed by a processor, cause the processor to perform operations comprising:

performing a test of the stacked memory device using a BIST (built-in self-test) circuit of the stacked memory device, the test of the stacked memory device utilizing the scrambled data.