Memory devices and formation methods

• US 9,190,265 B2
• Filed: 04/08/2014
• Issued: 11/17/2015
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun, Sandhu, Gurtej S.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US14/247,653
• Publication Number:
  US 20140220763A1
• Time in Patent Office: 588 Days
• Field of Search: 438/237, 438/455, 438/459, 257/379, 257/E21.123, 257/E21.645, 257/E27.033
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02225 characterised by the process for the formation of the insulating layer
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/801 Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Claims

1. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate, the forming of the plurality of cross-point memory cells comprising patterning through the doped region of the second substrate to form a plurality of conductive lines of the cross-point memory cells, the plurality of conductive lines comprising the doped region exhibiting the second conductivity type.

2. The method of claim 1 wherein the insulator material is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

3. The method of claim 1 wherein the semiconductor material comprises a monocrystalline material.

4. The method of claim 1 wherein the bonding comprises providing an adhesion material between the second substrate and the insulator material of the first substrate.

5. The method of claim 4 wherein the adhesion material is electrically insulative.

6. The method of claim 1 wherein the bonding occurs at no higher than 400°

C.

7. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material;

after the removing, forming a plurality of cross-point memory cells within the second substrate; and

the interconnect exhibiting a property such that, if exposed to at least one operating condition used in the activating, a physical structure of the interconnect would be altered.

8. The method of claim 7 wherein the at least one operating condition is temperature greater than 400°

C., the activating comprising heating to greater than 400°

C.

9. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate, the bonding comprising bonding the doped region to the insulator material;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate.

10. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate, the bonding comprising bonding the second substrate directly to the insulator material of the first substrate;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate.

11. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate, the bonding comprising providing an adhesion material between the second substrate and the insulator material of the first substrate, the adhesion material being electrically conductive;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate.

12. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate, the bonding comprising forming a bond interface between the second substrate and the insulator material of the first substrate, the bond interface being continuous and substantially planar;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate.

13. A method of forming a multilevel integrated circuit, comprising:

forming circuit components onto a first substrate;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof;

activating the dopant by heating to greater than 400°

C. to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate at no higher than 400°

C.;

removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and

after the removing, forming a plurality of cross-point memory cells within the second substrate, the forming of the plurality of cross-point memory cells comprising patterning through the doped region of the second substrate to form a plurality of conductive lines of the cross-point memory cells, the plurality of conductive lines comprising the doped region exhibiting the second conductivity type.

14. The method of claim 13 wherein the bonding comprises forming a bond interface between the second substrate and the insulator material of the first substrate, the bond interface being continuous and substantially planar.

15. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise semiconductor material having a dopant therein;

activating the dopant within the semiconductor material of the second substrate;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate;

after the bonding, forming circuit components in the second substrate that comprise the activated dopant within the semiconductor material of the second substrate; and

a circuit component of the first substrate exhibiting a property such that, if exposed to at least one operating condition used in the activating, a physical structure of said circuit component of the first substrate would be altered.

16. The method of claim 15 wherein the at least one operating condition is temperature greater than 400°

C., the activating comprising heating to greater than 400°

C.

17. A method of forming a multi-level integrated circuit, comprising:

forming circuit components onto a first substrate;

forming an electrical insulator material over the circuit components of the first substrate;

processing a second substrate to comprise semiconductor material having a dopant therein;

activating the dopant within the semiconductor material of the second substrate;

after activating the dopant, bonding the second substrate to the insulator material of the first substrate, the bonding comprising providing an electrically conductive adhesion material between the second substrate and the insulator material of the first substrate; and

after the bonding, forming circuit components in the second substrate that comprise the activated dopant within the semiconductor material of the second substrate.