Semiconductor device and method of fabricating the same

• US 9,190,272 B1
• Filed: 07/15/2014
• Issued: 11/17/2015
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, CheolWoo, Lee, Kwangyul, Won, Seokjun, Lee, Jeongeon, Jung, HyungSuk
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/331,715
• Time in Patent Office: 490 Days
• Field of Search: 438/275
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a substrate including a first region and a second region;

forming dummy gate patterns on the substrate, each of the dummy gate patterns comprising a first gate insulating layer, a dummy layer, and a hard mask;

forming an interlayer insulating layer on the substrate to expose top surfaces of the dummy gate patterns;

removing the hard mask and the dummy layer to form a first trench and a second preliminary trench exposing the first gate insulating layer on the first and second regions, respectively;

forming a photoresist pattern on the first region provided with the first trench to expose the second preliminary trench on the second region;

removing a portion of the first gate insulating layer from the second preliminary trench to form a second trench exposing a portion of the substrate;

cleaning the portion of the substrate exposed by the second trench using an oxide etching solution;

removing the photoresist pattern from the first region;

forming a second gate insulating layer on the portion of the substrate exposed by the second trench;

forming gate electrodes on the first and second gate insulating layers; and

forming spacers after the forming the dummy gate patterns and before the forming the interlayer insulating layer, wherein

the spacers contact sidewalls of the dummy gate patterns,

the removing the portion of the first gate insulating layer from the second preliminary trench includes partially etching a sidewall of the spacers on the second region without etching the spacers on the first region, and

the sidewall of the spacers on the second region is tapered compared to a sidewall of the spacers on the first region after the removing the portion of the first gate insulating later from the second preliminary trench.

2. The method of claim 1, wherein the first gate insulating layer is formed to be thicker than the second gate insulating layer.

3. The method of claim 2, wherein the first and second gate insulating layers are formed using a dry oxidation process or a radical oxidation process.

4. The method of claim 1, wherein the dummy layer comprises polysilicon.

5. The method of claim 1, wherein the hard mask comprises silicon nitride.

6. The method of claim 1, wherein the spacers comprise silicon nitride.

7. The method of claim 1, wherein the removing of the portion of the first gate insulating layer is performed by a chemical oxide removal (COR) process using HF gas and NH₃ gas.

8. The method of claim 1, wherein the oxide etching solution contains HF solution or buffered oxide etchant (BOE) solution.

9. The method of claim 1, wherein the gate electrodes comprise at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or mixtures thereof.

10. The method of claim 1, further comprising forming high-k dielectric patterns between the first and second gate insulating layers and the gate electrodes.

11. The method of claim 10, wherein the high-k dielectric pattern comprises at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

12. The method of claim 1, wherein the second trench is formed to have a top width larger than a bottom width thereof.

13. The method of claim 1, wherein the forming of the gate electrodes comprises filling the first and second trenches with a metal layer and performing a planarization process on the metal layer.

14. The method of claim 13, wherein the planarization process is performed using an etch-back process or a chemical mechanical polishing (CMP) process.

15. The method of claim 1, wherein

the forming dummy gate patterns includes forming the first gate insulating layer directly on the substrate,

the forming gate electrodes includes forming the gate electrodes directly on the first and second gate insulating layers, and

the first and second gate insulating layer are single layers respectively.

16. The method of claim 1, wherein the removing the hard mask and the dummy layer includes removing an entire portion of the hard mask.