Multi-die sensor device

• US 9,190,352 B2
• Filed: 11/21/2013
• Issued: 11/17/2015
• Est. Priority Date: 11/21/2013
• Status: Active Grant

• Current Assignee: Chip Packaging Technologies, LLC
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Tiu, Kong Bee, Lau, Teck Beng, Lo, Wai Yew
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US14/086,942
• Publication Number:
  US 20150137279A1
• Time in Patent Office: 726 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01L 19/141 Monolithic housings, e.g. molded or one-piece housings
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.

Claims

1. A semiconductor device, comprising:

a lead frame having a flag and a plurality of leads surrounding the flag, wherein the plurality of leads comprises at least one normal lead and at least one dummy lead that has a first wire bonding area formed in a first plane and a second wire bonding area formed in a second plane, wherein the first plane is down-set from the second plane;

a first die attached on a top surface of the flag and electrically connected to the first wire bonding area of the dummy lead with a first bond wire;

a molding material encapsulating the first die, the first bond wire and the first wire bonding area of the dummy lead, wherein a cavity is formed in the molding material above the first die with an opening, and wherein the second wire bonding area of the dummy lead is exposed in the cavity, and is not lower than a bottom surface of the cavity; and

a second die attached on the bottom surface of the cavity and electrically connected to the second wire bonding area of the dummy lead with a second bond wire.

2. The semiconductor device of claim 1, further comprising:

a gel material disposed on a top surface of the second die; and

a lid with a hole attached over the opening in the cavity such that the lid covers the second die, the second bond wire and the gel material.

3. The semiconductor device of claim 1, further comprising:

a third bond wire electrically connecting the first die to the normal lead.

4. The semiconductor device of claim 1, further comprising:

a third die attached on a top surface of the first die and electrically connected to the first die with a fourth bond wire.

5. The semiconductor device of claim 1, wherein a bottom surface of the flag is exposed from the molding material.

6. The semiconductor device of claim 1, wherein an outer part of the dummy lead exposed out of the molding material is trimmed off.

7. A semiconductor device, comprising:

a lead frame having a flag, a plurality of leads surrounding the flag and at least one tie bar extending outward from the flag, wherein the tie bar includes a first wire bonding area formed in a first plane and a second wire bonding area formed in a second plane, wherein the first plane is down-set from the second plane;

a first die attached on a top surface of the flag and electrically connected to the first wire bonding area of the tie bar with a first bond wire;

a molding material encapsulating the first die, the first bond wire and the first wire bonding area of the tie bar, wherein

a cavity is formed in the molding material above the first die with an opening, and wherein the second wire bonding area of the tie bar is exposed in the cavity, and is not lower than a bottom surface of the cavity; and

a second die attached on the bottom surface of the cavity and electrically connected to the second wire bonding area of the tie bar with a second bond wire.

8. The semiconductor device of claim 7, further comprising:

a gel material disposed on a top surface of the second die; and

a lid with a hole attached over the opening in the cavity that covers the second die, the second bond wire and the gel material.

9. The semiconductor device of claim 7, further comprising:

a third bond wire electrically connecting the first die to one of the plurality of leads.

10. The semiconductor device of claim 7, further comprising:

a third die attached on a top surface of the first die and electrically connected to the first die with a fourth bond wire.