Method and system for heterogeneous substrate bonding for photonic integration

• US 9,190,400 B2
• Filed: 12/19/2013
• Issued: 11/17/2015
• Est. Priority Date: 10/13/2009
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Krasulick, Stephen B., Dallesasse, John
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): FORTICH, RODOLFO D
• Application Number:
  US14/135,006
• Publication Number:
  US 20140179036A1
• Time in Patent Office: 698 Days
• Field of Search: 438/26, 438/64, 438/456, 438/28, 438/34
• US Class Current: 1/1
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12147 Coupler
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/0237 by soldering
• CPC Class Codes: H01S 5/1003 Waveguide having a modified shape along the axis, e.g. branched, curved, tapered, voids

Abstract

A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.

Claims

1. A method of fabricating a hybrid integrated optical device, the method comprising:

providing a substrate comprising a silicon layer;

providing a compound semiconductor device;

forming a bonding region disposed between the silicon layer and the compound semiconductor device, wherein the bonding region comprises;

a metal-semiconductor bond at a first portion of the bonding region, wherein the metal-semiconductor bond includes a first pad bonded to the silicon layer, a bonding metal bonded to the first pad, and a second pad bonded to the bonding metal and the compound semiconductor device; and

an interface assisted bond at a second portion of the bonding region, wherein the interface assisted bond includes an interface layer positioned between the silicon layer and the compound semiconductor device, wherein the interface assisted bond provides an ohmic contact between the silicon layer and the compound semiconductor device.

2. The method of claim 1 wherein the substrate comprises a silicon on insulator wafer including a silicon substrate, an oxide layer disposed on the silicon substrate, and the silicon layer disposed on the oxide layer.

3. The method of claim 1 wherein the compound semiconductor device comprises an InP semiconductor laser.

4. The method of claim 3 wherein the second portion of the bonding region is substantially free from the interface layer at a position adjacent an active region of the InP semiconductor laser.

5. The method of claim 1 wherein the first pad and the second pad comprise at least one of Ti or Au.

6. The method of claim 1 wherein the interface layer comprises In_xPd_y.

7. The method of claim 6 wherein x=0.7 and y=0.3.

8. The method of claim 1 wherein a thickness of the interface layer is less than 50 Å

.

9. The method of claim 1 wherein forming the bonding region disposed between the silicon layer and the compound semiconductor device comprises performing a bonding process at a temperature ranging from about 350°

C. to about 500°

C.

10. The method of claim 9 wherein the temperature ranges from about 400°

C. to about 450°

C.

11. A method of fabricating a composite integrated optical device, the method comprising:

providing a substrate comprising a silicon layer;

forming a waveguide in the silicon layer;

forming a layer comprising a metal material coupled to the silicon layer;

providing an optical detector;

forming a metal-assisted bond between the metal material and a first portion of the optical detector; and

forming a direct semiconductor-semiconductor bond between the waveguide and a second portion of the optical detector.

12. The method of claim 11 wherein the substrate comprises a silicon on insulator wafer including a silicon substrate, an oxide layer disposed on the silicon substrate, and

the silicon layer disposed on the oxide layer.

13. The method of claim 11 wherein the optical detector comprises an APD receiver.

14. The method of claim 13 wherein forming the layer comprising the metal material comprises:

depositing the metal material; and

patterning the metal material to expose the silicon layer in a predetermined spatial pattern.

15. The method of claim 11 wherein the metal material comprises In_xPd_y.

16. The method of claim 15 wherein x=0.7 and y=0.3.

17. The method of claim 11 wherein a thickness of the metal material is less than 100 Å

.

18. The method of claim 11 wherein forming the metal-assisted bond and forming the direct semiconductor-semiconductor bond comprises performing a bonding process at a temperature ranging from about 350°

C. to about 500°

C.

19. The method of claim 18 wherein the temperature ranges from about 400°

C. to about 450°

C.