Three-dimensional offset-printed memory

• US 9,190,412 B2
• Filed: 08/30/2012
• Issued: 11/17/2015
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US13/599,085
• Publication Number:
  US 20130058146A1
• Time in Patent Office: 1,174 Days
• Field of Search: 365/51, 365/230.06
• US Class Current: 1/1
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask-programmed read-only memory (3D-MPROM), it has a lower data-mask count and thereby a lower data-mask cost. The mask-patterns for different memory levels/bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to said data-mask. Accordingly, data-patterns are printed into different memory levels/bits-in-a-cell from a same data-mask.

Claims

1. A three-dimensional offset-printed memory (3D-oP), comprising:

a semiconductor substrate;

a plurality of vertically stacked memory levels stacked above and coupled to said substrate, each of said memory levels comprising at least a data-coding layer, whose pattern represents a data-array;

wherein all devices in a same 3D-oP batch with said 3D-oP have a same data-array set; and

at least two devices in said batch have different data-array sequences.

2. The 3D-oP according to claim 1, further comprising a configurable-I/O means for configuring the input and/or output of said memory based on the data-array sequence in said memory.

3. The 3D-oP according to claim 2, wherein said configurable-I/O means further comprises a storage means for storing the information related to the data-array sequence.

4. The 3D-oP according to claim 3, wherein said storage means is a non-volatile writable memory.

5. The 3D-oP according to claim 1, wherein said 3D-oP batch further includes first and second memory devices:

said first memory device comprises first and second memory levels, said second memory level stacked above said first memory level, said first memory level storing a first data-array, said second memory level storing a second data-array; and

said second memory device comprises third and fourth memory levels, said fourth memory level stacked above said third memory level, said third memory level storing said second data-array, said fourth memory level storing said first data-array.

6. The 3D-oP according to claim 5, wherein each of said first and second memory devices further comprises a configurable-I/O means for changing the input of said memory device based on the data-array sequence.

7. The 3D-oP according to claim 1, wherein said 3D-oP batch further includes first and second memory devices:

said first memory device comprises a first memory level, said first memory level storing first and second data-arrays, wherein said second data-array is located above said first data-array; and

said second memory device comprises a second memory level, said second memory level storing said first and second data-arrays, wherein said first data-array is located above said second data-array.

8. The 3D-oP according to claim 7, wherein said each of said first and second memory devices further comprises a configurable-I/O means for changing the output of said memory device based on the data-array sequence.

9. The 3D-oP according to claim 1 belonging to a three-dimensional memory package, wherein said memory package comprises a plurality of vertically stacked 3D-oP dice.