Super junction semiconductor device and method for manufacturing the same

• US 9,190,469 B2
• Filed: 04/01/2014
• Issued: 11/17/2015
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Cho, Moon Soo, Jun, Kwang Yeon, Choi, Chang Yong, Woo, Hyuk, Kwon, Soon Tak
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/242,359
• Publication Number:
  US 20150076600A1
• Time in Patent Office: 595 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Claims

1. A super junction semiconductor device comprising:

an n-type semiconductor region disposed in a substrate;

two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate;

a p-type body region disposed on at least one of the p-type semiconductor regions; and

a source region disposed in the p-type body region,

wherein a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions are implanted with an n-type dopant.

2. The super junction semiconductor device of claim 1, further comprising:

a drain electrode electrically connected to the substrate; and

a source electrode disposed on the p-type body region and the source region.

3. The super junction semiconductor device of claim 1, wherein a net quantity of charge of the n-type semiconductor region and a quantity of charges of the p-type semiconductor region are balanced.

4. The super junction semiconductor device of claim 1, wherein a lower region of the p-type semiconductor regions in a vertical direction has the lowest p-type doping concentration in the p-type semiconductor regions.

5. The super junction semiconductor device of claim 1, wherein a lower region of the n-type semiconductor region in a vertical direction has a doping concentration higher than a doping concentration of an upper region of the n-type semiconductor region.

6. The super junction semiconductor device of claim 1, wherein the p-type semiconductor regions include a first region disposed at a lower end and a second region disposed at an upper end, and the first region and the second region have different widths.

7. The super junction semiconductor device of claim 6, wherein the width of the first region at the lower end is smaller than the width of the second region at the upper end.

8. The super junction semiconductor device of claim 7, wherein the doping concentration of the n-type semiconductor region is constant above the lower end of the n-type semiconductor region having the smaller width.

11. The super junction semiconductor device of claim 1, wherein the n-type dopant locally decreases the p-type doping concentration in the lower ends of the p-type semiconductor region through counter-doping and locally increases the n-type doping concentration in the lower end of the n-type semiconductor region.

9. A semiconductor device comprising:

a drain region;

a n-type semiconductor region disposed above the drain region;

two or more p-type semiconductor regions disposed alternately to the n-type semiconductor region in a direction parallel to the drain region; and

a source region disposed above the p-type semiconductor region,

wherein the p-type semiconductor region has a first region adjacent to the drain region, and a second region adjacent to the source region,

wherein the second region has substantially a same width along a depth of the second region and the first region has a width smaller than the width of the second region.

10. The semiconductor device according to claim 9,

wherein a doping concentration of the n-type semiconductor region adjacent to the drain region is higher than a doping concentration of the n-type semiconductor region adjacent to the source region, and

a doping concentration of each of the p-type semiconductor regions adjacent to the drain region is lower than a doping concentration of the n-type semiconductor region adjacent to the source region.

12. The semiconductor device of claim 9, wherein a height of the p-type semiconductor region with smaller width is between about 50% and about 5% of a height of the p-type semiconductor region.

13. The semiconductor device of claim 9, wherein the p-type semiconductor region and the n-type semiconductor adjacent to the drain region are implanted with an n-type dopant.

14. The semiconductor device of claim 9, wherein the n-type dopant locally decreases the p-type doping concentration in the lower ends of the p-type semiconductor region through counter-doping and locally increases the n-type doping concentration in the lower end of the n-type semiconductor region.