Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance

• US 9,190,486 B2
• Filed: 11/20/2012
• Issued: 11/17/2015
• Est. Priority Date: 11/20/2012
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cai, Xiuyu, Zhang, Xunyuan
• Primary Examiner(s): Li, Meiya
• Assistant Examiner(s): Albrecht, Peter M
• Application Number:
  US13/682,331
• Publication Number:
  US 20140138779A1
• Time in Patent Office: 1,092 Days
• Field of Search: 438/197, 438/299, 438/595, 438/257, 438/300, 438/303, 438/421, 438/422, 438/619, 438/700, 438/738, 257/E21.409, 257/E29.255, 257/E21.19
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Claims

1. A method for fabricating an integrated circuit, comprising:

forming a sacrificial gate structure over a semiconductor substrate,

wherein a top surface of the sacrificial gate structure is located a first distance from the semiconductor substrate;

forming a spacer around the sacrificial gate structure;

depositing a dielectric material over the spacer and the semiconductor substrate;

selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material, wherein the trench is bounded by a trench surface, wherein a top end of the trench surface is located a second distance from the semiconductor substrate, and wherein the second distance is greater than the first distance; and

depositing a replacement spacer material along the trench surface and merging an upper region of the replacement spacer material to form a merged upper region of the replacement spacer material, to enclose a void within the replacement spacer material and to partially enclose a pocket within the replacement spacer material, wherein the void is formed around at least one sidewall of the sacrificial gate structure, the pocket is formed directly over and overlaps the sacrificial gate structure, and the pocket does not overlap the void.

2. The method of claim 1, further comprising:

etching a portion of the merged upper region of the replacement spacer material and exposing the sacrificial gate structure;

removing the sacrificial gate structure to form an opening adjacent the replacement spacer material; and

forming a replacement gate structure in the opening, wherein a top surface of the replacement gate structure is located a third distance from the semiconductor substrate, and wherein the third distance is greater than the first distance.

3. The method of claim 1, further comprising:

depositing a liner over the spacer and over the semiconductor substrate to define a spacer portion of the liner and at least one substrate portion of the liner, wherein depositing the dielectric material over the spacer and the semiconductor substrate comprises depositing the dielectric material over the liner.

4. The method of claim 3, wherein selectively etching the spacer to form the trench comprises selectively etching the spacer and the spacer portion of the liner to form the trench, and wherein the at least one substrate portion of the liner remains underlying the dielectric material.

5. The method of claim 2, further comprising:

recessing an upper portion of the replacement gate structure to form a recess;

depositing a gate cap material in the recess; and

forming a self-aligned contact adjacent the replacement spacer material.

6. The method of claim 3, wherein depositing the liner to define the at least one substrate portion of the liner comprises depositing the liner to define a first substrate portion of the liner and a second substrate portion of the liner, and wherein depositing the replacement spacer material to enclose the void within the replacement spacer material comprises enclosing the void directly between the first substrate portion of the liner and the second substrate portion of the liner.

7. The method of claim 1, wherein selectively etching the spacer to form the trench comprises partially etching the spacer.

8. The method of claim 1, further comprising:

etching a portion of the merged upper region of the replacement spacer material to form an upper trench exposing the sacrificial gate structure, wherein the upper trench is defined by sidewalls formed by an unetched portion of the merged upper region of the replacement spacer material;

removing the sacrificial gate structure to form an opening adjacent the replacement spacer material; and

forming a replacement gate structure in the opening and in the upper trench.

9. A method for fabricating an integrated circuit, comprising:

forming a sacrificial gate structure over a semiconductor substrate;

depositing a spacer material adjacent and over the sacrificial gate structure to enclose a void within the spacer material and to partially enclose a pocket within the spacer material, wherein the void is formed around at least one sidewall of the sacrificial gate structure, the pocket is formed directly over and overlaps the sacrificial gate structure, and the pocket does not overlap the void, and wherein depositing the spacer material adjacent the sacrificial gate structure to enclose the void within the spacer material comprises forming a hollow spacer;

etching the spacer material over the sacrificial gate structure to form an upper trench bounded by the sacrificial gate structure and an unetched portion of the spacer material;

removing the sacrificial gate structure to form an opening adjacent the hollow spacer; and

forming a replacement gate structure in the opening.

10. The method of claim 9, further comprising:

defining a lower trench adjacent the sacrificial gate structure, wherein the lower trench is bounded by a trench surface of the lower trench, wherein a top surface of the sacrificial gate structure is located a first distance from the semiconductor substrate, wherein a top end of the trench surface of the lower trench is located a second distance from the semiconductor substrate, wherein the second distance is greater than the first distance, and wherein depositing the spacer material adjacent the sacrificial gate structure comprises depositing the spacer material in the lower trench.

11. The method of claim 9, further comprising:

depositing a gate dielectric layer over the semiconductor substrate, wherein forming the sacrificial gate structure comprises forming the sacrificial gate structure over the gate dielectric layer, and wherein depositing the spacer material comprises depositing the spacer material over the gate dielectric layer and enclosing the void directly over the gate dielectric layer.

12. The method of claim 10, further comprising:

depositing a gate dielectric layer on the semiconductor substrate, wherein forming the sacrificial gate structure comprises forming the sacrificial gate structure on a gate portion of the gate dielectric layer, wherein depositing the spacer material comprises depositing the spacer material on a spacer portion of the gate dielectric layer, and wherein the void is positioned directly over the spacer portion of the gate dielectric layer.

13. The method of claim 9, wherein forming the sacrificial gate structure comprises forming the sacrificial gate structure with a top surface of the sacrificial gate structure located a first distance from the semiconductor substrate, wherein forming the replacement gate structure comprises forming the replacement gate structure with a top surface of the replacement gate structure located a second distance from the semiconductor substrate, and wherein the second distance is greater than the first distance.

14. The method of claim 9, wherein forming the replacement gate structure in the opening comprises forming the replacement gate structure in the opening and in the upper trench.

15. The method of claim 9, further comprising:

recessing an upper portion of the replacement gate structure to form a recess;

depositing a gate cap material in the recess; and

forming a self-aligned contact adjacent the hollow spacer.

16. A method for fabricating an integrated circuit, comprising:

forming a sacrificial gate structure over a semiconductor substrate;

depositing a spacer material adjacent and over the sacrificial gate structure to enclose a void within the spacer material and to partially enclose a pocket within the spacer material, wherein the void is formed around at least one sidewall of the sacrificial gate structure, the pocket is formed directly over and overlaps the sacrificial gate structure, and the pocket does not overlap the void;

removing the sacrificial gate structure to form an opening adjacent the spacer material; and

forming a replacement gate structure in the opening.

17. The method of claim 16, further comprising:

selectively etching a portion of the spacer material to form an upper trench before removing the sacrificial gate structure, the portion of the spacer material being disposed over the sacrificial gate structure and partially enclosing the pocket, wherein the upper trench is defined by sidewalls formed by an unetched portion of the spacer material.

18. The method of claim 17, wherein forming the replacement gate structure comprises forming the replacement gate structure in the opening and in the upper trench, wherein the sacrificial gate structure has a first height, and wherein the replacement gate structure has a second height greater than the first height.

19. The method of claim 16, further comprising:

defining a trench adjacent the sacrificial gate structure, wherein the trench is bounded by a trench surface, and wherein the pocket is located inside the trench.

20. The method of claim 16, further comprising:

depositing a dielectric material over the sacrificial gate structure and the semiconductor substrate, wherein a top surface of the dielectric material is positioned above a top surface of the sacrificial gate structure; and

defining a trench in the dielectric material and adjacent the sacrificial gate structure, wherein the pocket is located inside the trench, directly above the top surface of the sacrificial gate structure and lower than the top surface of the dielectric material.