Semiconductor device

• US 9,190,504 B2
• Filed: 09/19/2014
• Issued: 11/17/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Kawashiri, Satoshi
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/491,114
• Publication Number:
  US 20150084093A1
• Time in Patent Office: 424 Days
• Field of Search: 257/330, 257/333, 257139-140
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66007 Multistep manufacturing processes
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Claims

1. A semiconductor device comprising:

a first semiconductor region, which has a first conductivity type;

a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region;

a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region;

a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region;

an insulation film, which is arranged on an inner wall of a recess extending from an upper surface of the fourth semiconductor region and penetrate the fourth semiconductor region and the third semiconductor region to reach the second semiconductor region;

a control electrode, which is arranged on a region of the insulation film on a side surface of the recess, the region facing a side surface of the third semiconductor region;

a first main electrode, which is electrically connected to the first semiconductor region;

a second main electrode, which is electrically connected to the fourth semiconductor region; and

a bottom electrode, which is arranged on the insulation film with being separated from the control electrode on a bottom surface of the recess and is electrically connected to the second main electrode,

wherein a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses, as viewed from a plan view.

2. The semiconductor device according to claim 1,

wherein a width of the bottom electrode facing the bottom surface of the recess is wider than a width of the control electrode facing the bottom surface of the recess.

3. The semiconductor device according to claim 1,

wherein a width of the bottom electrode facing the bottom surface of the recess is larger than a thickness of the bottom electrode in a film thickness direction.

4. The semiconductor device according to claim 1,

wherein a position of a lower surface of the control electrode is lower than a position of an upper surface of the bottom electrode.

5. The semiconductor device according to claim 1,

wherein a width of the bottom electrode facing the bottom surface of the recess is larger than an interval between the bottom electrode and the control electrode along the bottom surface of the recess.

6. The semiconductor device according to claim 1,

wherein a width of the recess is larger than a depth of the recess and is 3 to 20 μ

m.

7. The semiconductor device according to claim 1, further comprising:

a connection recess, which has at least an intersection part formed to penetrate the third semiconductor region and to reach the second semiconductor region and extending in a direction intersecting with an extension direction of the recess, the recess being connected at the intersection part,

wherein the control electrodes arranged in a plurality of recesses arranged in parallel are connected each other by a conductive film arranged in the connection recess.

8. The semiconductor device according to claim 7,

wherein the connection recess further has a parallel part arranged in parallel with the recess.

9. The semiconductor device according to claim 7,

wherein a width of the connection recess is narrower than a width of the recess.

10. The semiconductor device according to claim 7,

wherein a width of the connection recess is wider than a width of the recess.

11. The semiconductor device according to claim 1,

wherein a width of the recess is 3 μ

m to 15 μ

m,

wherein a depth of the recess is 2 μ

m to 10 μ

m,

wherein a thickness of the second semiconductor region is 40 μ

m to 140 μ

m and a specific resistance of the second semiconductor region is 10 Ω

cm to 150 Ω

cm.

12. A semiconductor device comprising:

a first semiconductor region, which has a first conductivity type;

a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region;

a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region;

a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region;

an insulation film, which is arranged on an inner wall of a recess extending from an upper surface of the fourth semiconductor region and penetrates the fourth semiconductor region and the third semiconductor region to reach the second semiconductor region;

a control electrode, which is arranged on a region of the insulation film on a side surface of the recess, the region facing a side surface of the third semiconductor region;

a bottom electrode, which is arranged on the insulation film with being separated from the control electrode on a bottom surface of the recess;

a first main electrode, which is electrically connected to the first semiconductor region;

an interlayer insulation film arranged on the control electrode and the bottom electrode; and

a second main electrode, which is arranged on the third semiconductor region and the fourth semiconductor region, above the control electrode and the bottom electrode, with interposing the interlayer insulation film, and electrically connected to the fourth semiconductor region and the bottom electrode,

wherein an area of the recess is larger than an area of a semiconductor region between the adjacent recesses, as viewed from a plan view.

13. The semiconductor device according to claim 12,

wherein an area of the bottom electrode facing the bottom surface of the recess is larger than an area of the control electrode facing the bottom surface of the recess.