High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices

• US 9,190,512 B2
• Filed: 01/27/2015
• Issued: 11/17/2015
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lee, Yeeheng, Chang, Hong, Kim, Jongoh, Lui, Sik, Yilmaz, Hamza, Bobde, Madhur, Calafut, Daniel, Chen, John
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US14/606,928
• Publication Number:
  US 20150145037A1
• Time in Patent Office: 294 Days
• Field of Search: 257/332
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T₂ that is larger than the thickness T₁ of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A MOSFET device, comprising:

a semiconductor substrate of a first conductivity type wherein the substrate includes a lightly doped drift region in a top portion of the substrate;

a body region of a second conductivity type formed in a top portion of the semiconductor substrate, wherein the second conductivity type is opposite the first conductivity type;

a plurality of active device structures formed from the semiconductor substrate and body region, wherein each active device structure comprises a gate electrode insulated with a gate oxide, wherein an upper portion of the gate oxide is a thickness T₁ and a bottom portion of the gate oxide is a thickness T₂, wherein T₂ is greater than T₁;

one or more source regions of the first conductivity type formed in a top portion of the body region proximate the gate electrode;

an insulative gate cap formed over each gate electrode, wherein a first insulating spacer is formed on the sidewalls of the insulative gate cap and a second insulating spacer is formed on the exposed side walls of the first insulating spacer,;

an insulative layer over a top surface of the body region;

a conductive source electrode layer formed over the insulative layer;

one or more electrical connections that connect the source electrode layer with the one or more source regions, wherein the one or more electrical connections are spaced apart from the gate cap by the first and second insulative spacers.

2. The MOSFET device of claim 1, wherein the first insulating spacer and the second insulating spacer are formed from the same material.

3. The MOSFET device of claim 2, wherein the first insulating spacer and the second insulating spacer are formed from a nitride material.

4. The MOSFET device of claim 1, wherein the second insulating spacer is resistant to a first etching process used for selectively etching the material that the first insulating spacer is made from, and wherein the first insulating spacer is resistant to a second etching process used for selectively etching the material that the second insulating layer is made from.

5. The MOSFET device of claim 4, wherein the first insulating spacer is an oxide material, and the second insulating spacer is a nitride material.

6. The MOSFET device of claim 1, further comprising:

one or more electrostatic discharge (ESD) protection features formed above the insulative layer.

7. The MOSFET device of claim 1, further comprising one or more gate pickup structures formed in the semiconductor substrate.

8. The MOSFET device of claim 1, further comprising a body clamp (BCL) structure.

9. The MOSFET device of claim 1, wherein the pitch of the active device structures is less than 0.6 microns.