Nonplanar device with thinned lower body portion and method of fabrication

• US 9,190,518 B2
• Filed: 05/08/2014
• Issued: 11/17/2015
• Est. Priority Date: 10/25/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Doyle, Brian S., Brask, Justin K., Chau, Robert S., Letson, Thomas A.
• Primary Examiner(s): Movva, Amar
• Application Number:
  US14/273,373
• Publication Number:
  US 20140239358A1
• Time in Patent Office: 558 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A nonplanar tri-gate transistor comprising:

a semiconductor body having;

a top surface opposite a bottom surface; and

a pair of laterally opposite sidewalls extending between the top surface and the bottom surface, wherein the laterally opposite sidewalls include a tapered portion that extends from the top surface to the bottom surface of the semiconductor body such that a distance between the laterally opposite sidewalls at the top surface is greater than a distance between the laterally opposite sidewalls at the bottom surface;

a gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the semiconductor body from the top surface to the bottom surface;

a gate electrode formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body; and

a pair of source/drain region formed in the semiconductor body on opposite sides of the gate electrode.

2. The nonplanar tri-gate transistor of claim 1 wherein the distance between the sidewalls at the bottom surface of the semiconductor body is approximately ½

to ⅔

of the distance between the sidewalls at the top surface of the semiconductor body.

3. The nonplanar tri-gate transistor of claim 1 wherein a distance between the sidewalls at a bottom portion of the semiconductor body is made sufficiently small so as to improve the short channel effects of the transistor.

4. The nonplanar tri-gate transistor of claim 1 wherein the distance between the laterally opposite sidewalls at the top surface of the semiconductor body is approximately 20-30 nm.

5. The nonplanar tri-gate transistor of claim 1 wherein a distance between the laterally opposite sidewalls near a bottom portion of the semiconductor body is approximately 10-15 nm.

6. The nonplanar tri-gate transistor of claim 1 wherein the tapered portion that extends from the top surface to the bottom surface of the semiconductor body is a facet.

7. The nonplanar tri-gate transistor of claim 1 wherein the semiconductor body comprises silicon.

8. The nonplanar tri-gate transistor of claim 1 wherein the distance between the sidewalls near the bottom surface of the semiconductor body is approximately 50-66% of the distance between the sidewalls at the top of the semiconductor body.

9. The nonplanar tri-gate transistor of claim 1 wherein the composition of the gate dielectric layer formed on the top surface is the same composition as the gate dielectric layer formed on the sidewalls.

10. The nonplanar tri-gate transistor of claim 1 wherein the gated dielectric layer is a continuous gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the semiconductor body.