Bridgeless boost power factor correction circuit for constant current input

• US 9,190,901 B2
• Filed: 05/03/2013
• Issued: 11/17/2015
• Est. Priority Date: 05/03/2013
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Cooper Technologies Company (Eaton Corporation PLC.)
• Inventors: Gumaer, Traver
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US13/887,205
• Publication Number:
  US 20140328097A1
• Time in Patent Office: 928 Days
• Field of Search: 323/222, 323/225, 323/268, 323/271, 323/272, 323/282, 323/285, 363/84, 363/89
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0085 Partially controlled bridges
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present disclosure provides techniques for power factor correction on a constant current system without the use of a diode rectifier bridge. In an example embodiment, the present disclosure provides a power factor correction circuit which includes two switching MOSFETs biased in opposite directions which operate during opposite half cycles of the input current. The power factor correction circuit generates an input voltage to match the phase of the input current. The input voltage is generated via charging and draining of an input capacitor by the MOSFETs. The MOSFETs are driven on a duty cycle synchronously associated with the input current wave form.

Claims

1. A bridgeless constant current power factor correction circuit, comprising:

an input capacitor configured to receive an input current from a constant current source and produce an input voltage;

a first switching device coupled to the input capacitor and the current source, wherein the first switching device is operable during a first half cycle of the input current and shorted during a second half cycle of the input current, and wherein when operable, the first switching device switches between an ON state and an OFF state;

a second switching device coupled to the input capacitor and the current source, wherein the second switching device is operable during the second half cycle of the input current and shorted during the first half cycle of the input current, and wherein when operable, the second switching device switches between the ON state and the OFF state;

a controller coupled to the first switching device and the second switching device, wherein the controller switches the first or second switching device between the ON state and the OFF state, depending on which half cycle the input current is in, wherein when one of the first or second switching devices is in the OFF state, the input capacitor charges and the input voltage rises, and when one of the first or second switching devices is in the ON state, the input capacitor drains and the input voltage drops; and

a DC output bus providing an output voltage, wherein the output voltage is a conditioned form of the input voltage, wherein the input voltage is in phase with the input current.

2. The bridgeless constant current power factor correction circuit of claim 1, wherein the first and second switching devices each comprises a switching MOSFET.

3. The bridgeless constant current power factor correction circuit of claim 1, wherein during the first half cycle, the first switching device is put in the ON state when the input voltage reaches a reference voltage, the reference voltage representing a desired power level of the output voltage.

4. The bridgeless constant current power factor correction circuit of claim 1, wherein the controller comprises a feedback controller, wherein the feedback controller receives and compares the output voltage and the reference voltage, wherein a feedback controller output increases when the output voltage is below the reference voltage and decreases when the output voltage is above the reference voltage.

5. The bridgeless power factor correction circuit of claim 4, wherein the feedback controller output is multiplied with a sine wave reference signal to obtain a synchronized reference signal, wherein the sine wave reference signal has a phase matching the phase of the input current.

6. The bridgeless power factor correction circuit of claim 5, wherein the controller further comprises a pulse width modulation generator, wherein the pulse width modulation generator generates a pulse width modulation signal from the synchronized reference signal, which drives the first and second switching devices.

7. The bridgeless power factor correction circuit of claim 1, further comprising:

a first transformer, wherein the first transformer provides the output voltage during the first half cycle of the input current; and

a second transformer, wherein the second transformer provides the output voltage during the second half cycle of the input current.

8. A bridgeless constant current power factor correction circuit, comprising:

an input capacitor configured to receive an input current from a constant current source and produce an input voltage, wherein the input current comprises a current waveform;

a first MOSFET switchable between an ON state and an OFF state when the input current is in a first half cycle;

a second MOSFET switchable between the ON state and the OFF state when the input current is in a second half cycle,

wherein when one of the first or second MOSFETs is in the OFF state, the input capacitor is charged from the input current and the input voltage rises, and when one of the first or second MOSFETs is in the ON state, the input capacitor is drained and the input voltage drops, wherein switching back and forth between the OFF state and the ON state gives the input voltage a substantially sinusoidal waveform, wherein the sinusoidal waveform is in phase with the input current waveform; and

a controller coupled to the first and second MOSFETs, wherein the controller controls switching of the first and second MOSFETs.

9. The bridgeless constant current power factor correction circuit of claim 8, further comprising:

an output bus coupled to the input capacitor via at least one voltage conditioning component, the output bus configured to provide an output voltage to a load, the output voltage being a conditioned form of the input voltage.

10. The bridgeless constant current power factor correction circuit of claim 9, wherein the controller monitors the input voltage and compares the input voltage to a reference voltage, and wherein the controller switches the first or second MOSFET from the OFF state to the ON state when the input voltage reaches the reference voltage.

11. The bridgeless constant current power factor correction circuit of claim 10, wherein the controller further comprises:

a feedback controller, wherein the feedback controller receives and compares the output voltage and the reference voltage, and produces an adjustment signal, wherein the adjustment signal increases when the output voltage is below the reference voltage and decreases when the output voltage is above the reference voltage, and wherein the adjustment signal is multiplied with a reference wave synchronized with the input current waveform, generating a control reference signal used to control switching of the first and second MOSFETs.

12. The bridgeless constant current power factor correction circuit of claim 11, wherein the controller further comprises:

a pulse width modulation (PWM) controller, wherein the PWM controller receives the control reference signal and generates a corresponding PWM signal, and wherein the PWM signal drives the switching of the first and second MOSFETs.

13. The bridgeless constant current power factor correction circuit of claim 8, further comprising:

a first transformer, wherein the first transformer receives the input voltage during the first half cycle of the input current and outputs an output voltage; and

a second transformer, wherein the second transformer receives the input voltage during the second half cycle of the input current and outputs the output voltage.

14. The bridgeless power factor correction circuit of claim 9, wherein the reference voltage comprises an amplitude representative of a desired power level.

15. The bridgeless power factor correction circuit of claim 8, wherein the first and second MOSFETs are biased in the opposite direction, wherein the second MOSFET is shorted when the first MOSFET is operational and the first MOSFET is shorted when the second MOSFET is operational.

16. A method of power factor correction on a constant current system, comprising:

receiving an input current from a constant current input source, the input current having a current waveform;

allowing an input capacitor to charge from the input current, wherein an input voltage formed at the input capacitor rises as the input capacitor charges;

determining if the input voltage reaches a reference voltage;

when the input current is in a first half cycle, switching a first switching device from a first state to a second state when the input voltage reaches the reference voltage;

when the input current is in a second half cycle, switching a second switching device from a first state to a second state when the input voltage reaches the reference voltage;

allowing the input capacitor to drain, wherein the input voltage drops as the input capacitor drains; and

shaping the input voltage to have a voltage waveform similar to the current waveform by controlling the switching of the first and second switching devices.

17. The method of power factor correction on a constant current system of claim 16, further comprising:

outputting the input voltage via an output bus.

18. The method of power factor correction on a constant current system of claim 17, further comprising:

filtering and rectifying the input voltage to produce a DC voltage; and

outputting the DC voltage via a DC output bus.

19. The method of power factor correction on a constant current system of claim 16, wherein during the first half cycle of the input current, the input voltage rises when the first switching device is in the first state and the input voltage drops when the first switching device is in the second state;

and

wherein during the second half cycle of the input current, the input voltage rises when the second switching device is in the first state and the input voltage drops when the second switching device is in the second state.

20. The method of power factor correction on a constant current system of claim 16, wherein the first and second switching devices each comprises a MOSFET.