Image sensor and imaging method with single shot compressed sensing

• US 9,191,026 B2
• Filed: 02/18/2013
• Issued: 11/17/2015
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Gamal, Abbas El, Oike, Yusuke
• Primary Examiner(s): Luu, Thanh
• Application Number:
  US13/769,471
• Publication Number:
  US 20140231620A1
• Time in Patent Office: 1,002 Days
• Field of Search: 250/208.1
• US Class Current: 1/1
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A CMOS image sensor includes a plurality of pixel elements arranged in a two-dimensional array, analog signal multiplexers, over-sampling A/D converters and an activation code generator. The sensor is configured to construct an image by using less number of A/D conversions, thereby reducing the power consumption of the sensor. The activation code generator generates a bit stream of random binary sequences which determine which A/D converter is activated. The image sensor offers digitally compressed data, the number of which is significantly less than the total number of pixels. Further, the image sensor not only reduces the power consumption of the A/D converters (by reducing the number of A/D conversions) but also reduces the I/O power consumption. An original image focused on the sensor is recovered from the compressed data by using principles of compressed sensing.

Claims

1. An image sensor comprising:

a plurality of pixel blocks including pixel elements, wherein each pixel element is configured to generate an analog signal corresponding to an intensity of light impinged on the pixel element;

a plurality of analog to digital, A/D, converters connected to each of the pixel block, wherein each A/D converter is configured to sample a corresponding average value of an input analog signal and convert the input analog signal to a digital signal based on a predetermined activation code that determines which A/D converters of the plurality of A/D converters are activated; and

a plurality of multiplexers, wherein each multiplexer is connected to the pixel block and the plurality of A/D converters and is configured to sequentially select and distribute the analog signal and subsequent analog signals obtained from the pixel block to the plurality of A/D converters in a cycle of A/D conversion.

2. The image sensor of claim 1, wherein the pixel block is connected to the multiplexer via a plurality of signal lines.

3. The image sensor of claim 1, wherein the plurality of A/D converters connected to each of the pixel block is less than a number of the pixel elements included in the pixel block.

4. The image sensor of claim 1, wherein the A/D converter is a sigma-delta modulator.

5. The image sensor of claim 1, wherein each A/D converter includes a filter that is configured to receive a string of binary bits and convert the string of binary bits to a digital value corresponding to the average value of the input analog signal.

6. The image sensor of claim 1, wherein the A/D converter comprises an accumulator configured to sum up the selected input analog signals.

7. The image sensor of claim 1, further comprises a row decoder that is configured to select a row of pixel elements from the pixel block and output the analog signal from each of the pixel element on the corresponding signal line.

8. The image sensor of claim 1, wherein the pixel element comprises a photo detector configured to generate photo-electrons corresponding to the intensity of light impinged on the pixel element.

9. The image sensor of claim 7, wherein the pixel element further comprises a transfer gate that transfers the photo-electrons to a capacitance node to generate a signal voltage level corresponding to the number of photo-electrons.

10. The image sensor of claim 9, wherein the pixel element further comprises

a reset gate configured to apply a reference voltage to the capacitance node;

an amplifier gate configured to amplify a voltage level of the capacitance node; and

a select gate configured to connect the amplifier gate to the signal line.

11. The image sensor of claim 9, wherein the select gate is shared by adjacent pixel elements.

12. The image sensor of claim 9, wherein the transfer gate and select gate of a plurality of pixel blocks are controlled simultaneously.

13. The image sensor of claim 1, wherein the activation code is generated by an activation code generator that comprises a plurality of pseudo-random shift registers.

14. The image sensor of claim 13, wherein the activation code is a random binary configuration.

15. The image sensor of claim 13, wherein the activation code generator comprises a memory for storing the bits of the activation code.

16. An image sensor comprising:

a plurality of pixel elements, wherein each pixel element is configured to generate an analog signal corresponding to an intensity of light impinged on the pixel element;

a plurality of analog to digital, A/D, converters, wherein each A/D converter is configured to sample a corresponding average value of an input analog signal and convert the input analog signal to a digital signal;

a plurality of multiplexers, wherein each multiplexer is connected to a pixel block and a first subset of the plurality of A/D converters and is configured to sequentially select and distribute the analog signal and following analog signals from the pixel block to the A/D converters in a cycle of A/D conversion, wherein each multiplexer of the plurality of multiplexers further comprises a plurality of sub-multiplexers connected to the same pixel block, each sub-multiplexer of the plurality of sub-multiplexers is connected to a second subset of the plurality of A/D converters.

17. The image sensor of claim 16, wherein the second subset of the plurality of A/D converters is smaller than the first subset of the plurality of A/D converters.

18. The image sensor of claim 16, wherein each sub-multiplexer processes a different input analog signal at the same time.

19. The image sensor of claim 16, wherein each sub-multiplexer randomly chooses an input analog signal from the plurality of input analog signals received by the corresponding multiplexer based on a random pattern generator.

20. An image processing method performed by an image sensor, the method comprising:

generating a plurality of analog signals from a plurality of pixel blocks, each pixel block including a plurality of pixel elements, each analog signal corresponding to an intensity of light impinged on the corresponding pixel element;

selecting by a decoder, a subset of analog signals generated by the generating;

multiplexing sequentially the subset of analog signals selected by the selecting and distributing the subset of analog signals to a plurality of analog to digital, A/D, converters connected to each of the pixel block;

generating a random activation code that determines which A/D converters of the plurality of A/D converters are activated; and

obtaining a digital read-out of the analog signals from the activated A/D converters.