Method and apparatus for iterative synchronization of two or more electronic devices

• US 9,191,907 B2
• Filed: 01/17/2014
• Issued: 11/17/2015
• Est. Priority Date: 10/11/2005
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Vleugels, Katelijn, Thompson, Barry
• Primary Examiner(s): YEUNG, MANG HANG
• Application Number:
  US14/158,241
• Publication Number:
  US 20140219269A1
• Time in Patent Office: 669 Days
• Field of Search: 370/324, 370/350, 370/395.62, 370/484, 370/503, 370507-520, 375354-376, 714/498
• US Class Current: 1/1
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00
• CPC Class Codes: H04J 3/0664 unidirectional timestamps
• CPC Class Codes: H04W 56/00 Synchronisation arrangements
• CPC Class Codes: H04W 56/002 Mutual synchronization

Abstract

Dynamic adjustment of offset between timebases of separated electronic circuits is provided based on an amount of time between synchronization events, wherein a synchronization event is an event involving communication across a separation between the separated electronic circuits in order to synchronize the timebases. The dynamic adjustment can be dynamically or adaptively adjusting a margin of error to account for drift that may have occurred since a prior synchronization event. Adjustments might be done by applying a learning sequence to quantify and adjust for static or slowly varying delays between the timebases and coordinating the timebases using output of the learning sequence.

Claims

1. A method comprising:

during a first synchronization event, obtaining, by a first electronic device in communication with a second electronic device, timing or synchronization information from the second electronic device;

determining a time offset between a first timebase of the first electronic device and a second timebase of the second electronic device using the timing or synchronization information;

adjusting the first timebase with the time offset; and

at an adjustment time occurring after the first synchronization event and before a second synchronization event, dynamically or adaptively adjusting the time offset based on an estimated timing error for a time period between the first synchronization event and the adjustment time, wherein the estimated timing error is determined without communication between the first electronic device and the second electronic device.

2. The method of claim 1, wherein the estimated timing error is determined at least in part by an amount of frequency drift introduced between first and second timers of the first and second electronic devices, respectively, during the time period.

3. The method of claim 2, wherein the dynamic or adaptive adjustment uses a learning sequence to quantify the frequency drift;

and dynamically or adaptively adjusts the time offset based on results of the learning sequence.

4. The method of claim 2, wherein the dynamic or adaptive adjustment uses a learning sequence to quantify static or varying delays;

and dynamically or adaptively adjusts the time offset based on results of the learning sequence.

5. The method of claim 2, wherein the first and second synchronization events are scheduled spaced in time to reduce frequency drift between the first and second timers.

6. The method of claim 2, wherein the first and second synchronization events are scheduled to make frequency drift a dominant component of the estimated timing error;

and using timing error data points collected during the time period to compute the frequency drift.

7. The method of claim 1, wherein dynamically or adaptively adjusting the time offset comprises dynamically or adaptively adjusting a margin of error for the time offset to account for the estimated timing error.

8. The method of claim 1, further comprising adjusting the time offset based on requirements of a communication system in which the first and second electronic devices are communicating.

9. The method of claim 1, further comprising:

scheduling a wake-up event at the first electronic device at the adjustment time.

10. The method of claim 1, wherein the first synchronization event is part of a data communication sequence between the first and second electronic devices.

11. The method of claim 1, wherein the estimated timing error is computed in the first electronic device.

12. The method of claim 1, wherein the time offset is stored in a table of the first or second electronic device, the table storing a plurality of static time offsets corresponding to different timing error sources.

13. The method of claim 1, wherein the first electronic device is a slave device and the second electronic device is a master device in a wireless communication system.

14. The method of claim 13, wherein the time offset is determined by the master device and sent to the slave device during the first synchronization event.

15. The method of claim 13, wherein the time offset is determined by the master device based on a master timer and slave timing information generated in the slave device and sent to the master device prior to the first synchronization event.

16. The method of claim 15, where the slave device ignores the time offset or uses the time offset to partially adjust the first timebase.

17. The method of claim 15, where the slave timing information accounts for a time delay between creation of a message including the slave timing information and sending of the message to the master device.

18. The method of claim 15, where the slave device sends the slave timing information in response to a poll signal sent by the master device.

19. The method of claim 15, where the master timer is derived from and synchronized to an interrupt timer.

20. The method of claim 13, wherein the master or slave device powers down circuitry after the first or second synchronization event.