Inverted 45 degree mirror for photonic integrated circuits

• US 9,195,007 B2
• Filed: 06/28/2012
• Issued: 11/24/2015
• Est. Priority Date: 06/28/2012
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Heck, John, Rong, Haisheng
• Primary Examiner(s): Ullah, Akm Enayet
• Assistant Examiner(s): MOONEY, MICHAEL P
• Application Number:
  US13/536,723
• Publication Number:
  US 20140003766A1
• Time in Patent Office: 1,244 Days
• Field of Search: 385/14, 385/31, 385/39, 385 49- 52, 438/31
• US Class Current: 1/1
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/26 Optical coupling means G02B6/36, G02B6/42 take precedence
• CPC Class Codes: G02B 6/42 Coupling light guides with opto-electronic elements
• CPC Class Codes: G02B 6/4208 using non-reciprocal elements or birefringent plates, i.e. quasi-isolators optical isolators per se G02F1/093, G02F1/0955
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching

Abstract

Inverted 45° semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45° semiconductor mirror functions to couple light between a plane in the PIC chip defined by thin film layers and a direction normal to a top surface of the PIC chip where it may be generated or collected by an off-chip component, such as a wire terminal. In an exemplary embodiment, a (110) plane of a cubic crystalline semiconductor may provide a 45° facet inverted relative to a (100) surface of the semiconductor from which light is to be emitted. In further embodiments, a (110) plane may be exposed by undercutting a device layer of a semiconductor on insulator (SOI) substrate. Alternatively, a pre-etched substrate surface may be bonded to a handling wafer, thinned, and then utilized for PIC waveguide formation.

Claims

1. A photonic integrated circuit (PIC), comprising:

a thin film dielectric layer disposed over a substrate;

a {100} crystalline device layer disposed over the thin film dielectric layer;

an optical waveguide formed in the device layer, wherein a {110} crystal plane of the device layer forms an end facet optically coupled the optical waveguide, wherein a sidewall of the thin film dielectric layer intersects the {110} crystal plane and wherein the substrate has an etch pit including a {110} crystal plane facet disposed below the {110} crystal plane of the device layer.

2. The PIC of claim 1, wherein the end facet has an index contrast with an interfacing media sufficient for the {110} crystal plane to induce internal reflection of an optical mode propagated by the waveguide into a <

100>

direction.

3. The PIC of claim 2, wherein the waveguide is to propagate the optical mode in a first of the <

100>

directions, toward or away from the end facet, and the end facet is to reflect the optical mode, into or from, a second of the <

100>

directions.

4. The PIC of claim 1, wherein the {110} crystal plane is reentrant from a top surface of the device layer.

5. The PIC of claim 4, further comprises an anti-reflective coating (ARC) layer disposed on the device layer and over the optical waveguide proximate to the end facet.

6. The PIC of claim 1, wherein the end facet is one side of a recess etched into the device layer, the recess having a plurality of sides defined by a plurality of {110} crystal planes.

7. The PIC of claim 1, further comprising an occlusion material disposed over the recess, wherein the occlusion material seals two opposite sides of the recess.

8. A photonic integrated circuit (PIC), comprising:

a thin film dielectric layer disposed over a substrate;

a crystalline semiconductor device layer disposed over the thin film dielectric layer; and

an optical waveguide formed in the device layer to propagate an optical mode in first directions substantially parallel to a top surface of the device layer,

wherein the optical waveguide comprises a crystalline end facet formed in the device layer to reflect the optical mode to and from second directions substantially normal to the top surface of the device layer,

wherein the end facet is a crystal plane oriented 45°

from the first and second directions,

wherein the end facet is one side of a recess etched into the device layer, the recess forming an opposing facet on an opposite side of the end facet.

9. The PIC of claim 8, wherein the top surface of the device layer is a {100} crystal plane and wherein the end facet is a {110} crystal plane of the device layer.

10. The PIC of claim 9, wherein the {110} crystal plane is reentrant from the top surface of the device layer and wherein the end facet has an index contrast with an interfacing media sufficient for the {110} crystal plane to induce internal reflection of the optical mode through the device layer.

11. A method of forming a mirror in a photonic integrated circuit (PIC), the method comprising:

forming an optical waveguide in a crystalline semiconductor device layer disposed over a thin film dielectric layer of a substrate;

etching a trench through the device layer;

etching a portion of the thin film dielectric layer exposed by the trench to create a recess extending between the portion of the thin film dielectric layer and the trench in the device layer; and

performing a crystallographic wet etch of the device layer exposed by the etching of the thin film dielectric to form a facet oriented 45°

from a top surface of the device layer that is optically coupled to the waveguide.

12. The method of claim 11, wherein the device layer is has cubic crystallinity with a {100} plane forming the top surface of the device layer and the facet is a {110} crystal plane.

13. The method of claim 12, wherein the device layer is silicon and wherein performing the crystallographic wet etch comprises exposing the device layer to an etchant solution comprising KOH and isopropyl alcohol (IPA).

14. The method of claim 11, wherein etching the trench further comprises:

forming a polygon in a mask material, the polygon having an edge normal to a <

100>

direction of the device layer; and

non-crystallographically etching the device layer exposed within the polygon.

15. A mobile computing platform comprising:

a processor;

a memory;

a display; and

an photonic integrated circuit (PIC) chip comprising;

a photodetector optically coupled to a first end of an optical waveguide formed in a device layer disposed over thin film dielectric layer of a substrate;

a crystalline end facet formed in the device layer and optically coupled to a second end of the optical waveguide to reflect light propagated from a direction substantially normal to the top surface of the device layer, to a direction that is propagated toward the photodetector, wherein the end facet is a crystal plane oriented 45°

from normal to the top surface.

16. The computing platform of claim 15, wherein the PIC chip further comprises a laser optically coupled to the end facet.

17. The computing platform of claim 15, wherein a {110} crystal plane of the device layer forms the end facet.