Semiconductor device, radio communication terminal using same, and clock frequency control method

• US 9,195,260 B2
• Filed: 12/22/2014
• Issued: 11/24/2015
• Est. Priority Date: 07/06/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuyama, Tsugio, Wakahara, Kohei, Fujigaya, Masaki, Irita, Takahiro
• Primary Examiner(s): WANG, ALBERT C
• Application Number:
  US14/579,068
• Publication Number:
  US 20150116010A1
• Time in Patent Office: 337 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Claims

1. A semiconductor device comprising:

a clock generation circuit that generates a clock signal;

an arithmetic circuit that operates according to the clock signal;

a storage circuit that is activated according to access from the arithmetic circuit;

a memory access detection unit that detects a number of accesses from the arithmetic circuit to the storage circuit and applies a weight to the number of accesses; and

a clock control circuit that lowers the frequency of the clock signal when a variation of the weighted number of accesses exceeds a variation threshold.

2. The semiconductor device according to claim 1, wherein the weight is a value for one access.

3. A clock frequency control method for a clock signal supplied to a semiconductor device with an arithmetic circuit that operates according to the clock signal and a storage circuit that is activated according to access from the arithmetic circuit, the clock frequency control method comprising:

detecting a number of accesses from the arithmetic circuit to the storage circuit;

applying a weight to the number of accesses; and

lowering a frequency of the clock signal when a variation of the weighted number of accesses exceeds a variation threshold.

4. The method according to claim 3, wherein the weight is a value for one access.