Flash/DRAM/embedded DRAM-equipped system and method
First Claim
1. An apparatus, comprising:
- NAND flash memory;
random access memory;
a first circuit for receiving DDR signals and outputting SATA signals; and
a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory;
said first circuit capable of being communicatively coupled to a third memory bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol;
said apparatus configured for;
receiving, over the third memory bus associated with the DDR protocol, a command that enables DDR protocol-compliant communication via the third memory bus for controlling the second circuit to cause one or more results that are undescribed in a specification of a JEDEC standard,after the receipt of the command, causing at least one of the results that is undescribed in the specification of the JEDEC standard, including causing particular data in the NAND flash memory to be written to the random access memory, utilizing the second circuit, andallowing a status in connection with the data.
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Abstract
An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including NAND flash memory and dynamic random access memory. Further included is a first circuit for receiving DDR signals and converting the DDR signals to SATA signals. The first circuit includes embedded dynamic random access memory. Also provided is a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals. The second circuit is communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the NAND flash memory via a second memory bus associated with a NAND flash protocol, and the dynamic random access memory.
476 Citations
78 Claims
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1. An apparatus, comprising:
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NAND flash memory; random access memory; a first circuit for receiving DDR signals and outputting SATA signals; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said first circuit capable of being communicatively coupled to a third memory bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; said apparatus configured for; receiving, over the third memory bus associated with the DDR protocol, a command that enables DDR protocol-compliant communication via the third memory bus for controlling the second circuit to cause one or more results that are undescribed in a specification of a JEDEC standard, after the receipt of the command, causing at least one of the results that is undescribed in the specification of the JEDEC standard, including causing particular data in the NAND flash memory to be written to the random access memory, utilizing the second circuit, and allowing a status in connection with the data.
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2. An apparatus, comprising:
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a plurality of memories including NAND flash memory and random access memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said apparatus configured for; receiving, at the first circuit via the first bus associated with the DDR protocol, a command that enables DDR protocol-compliant communication via the first bus for controlling the second circuit to cause one or more results that are undescribed in a specification of a JEDEC standard, after the receipt of the command, causing at least one of the results that is undescribed in the specification of the JEDEC standard, including writing particular information that is in one of the plurality of memories to another one of the plurality of memories, utilizing the second circuit, and providing a status in connection with the particular information. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
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77. A system, comprising:
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at least one processor; a driver; and a memory sub-system including; a plurality of memories including NAND flash memory and random access memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said at least one processor configured, under the control of the driver, for; sending, to the first circuit via the first bus associated with the DDR protocol, a command that is communicated in a way described in a specification of a JEDEC standard to cause one or more results that are undescribed in the specification of the JEDEC standard, including writing particular information that is in one of the plurality of memories to another one of the plurality of memories; and checking a status of the particular information.
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78. An apparatus, comprising:
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a plurality of memories including NAND flash memory, random access memory, and additional memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit communicatively coupled to the additional memory, and further capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said apparatus configured for; receiving, at the first circuit via the first bus associated with the DDR protocol, a command that is communicated in a way that is described in a specification of a JEDEC standard to cause one or more results that are undescribed in the specification of the JEDEC standard, the command including data of which a portion is used in connection with a corresponding command communicated via at least one of the second bus or the third bus; storing the command in the additional memory; after the receipt of the command, causing particular information that is in one of the plurality of memories to be written to another one of the plurality of memories, utilizing the second circuit; and providing a status on the particular information.
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Specification