Advanced management of a non-volatile memory

• US 9,195,592 B1
• Filed: 12/04/2013
• Issued: 11/24/2015
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Weingarten, Hanan, Maly, Igal, Segal, Avigdor
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US14/097,086
• Time in Patent Office: 720 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method of managing a non-volatile memory module, the method may include: allocating, by a memory controller, logically erased physical blocks of a non-volatile memory module to a spare block pool; allocating, by the memory controller, physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and controlling, by the memory controller, a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.

Claims

1. A method of managing a non-volatile memory module, the method comprising:

allocating, by a memory controller, logically erased physical blocks of a non-volatile memory module to a spare block pool;

allocating, by the memory controller, physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and

controlling, by the memory controller, a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.

2. The method according to claim 1 wherein the allocating of the logically erased physical blocks comprises:

initially allocating a predefined number of physical blocks to the spare block pool; and

further allocating to the spare block pool additional logically erased physical blocks.

3. The method according to claim 1 wherein the controlling of the utilization of the buffer blocks comprises controlling cleaning operations in response to a status of the buffer.

4. The method according to claim 1 further comprising controlling, by the memory controller, a utilization of a memory section of the non-volatile memory module that differs from the buffer by applying a block based buffer management scheme.

5. The method according to claim 4 comprising managing a logical block to physical block mapping data structure that maps logical blocks to mapped physical blocks.

6. The method according to claim 4 comprising receiving data sectors to be written to the non-volatile memory module and determining whether to write the data sectors to the buffer or to a mapped physical block.

7. The method according to claim 6 wherein the determining is responsive to a state of the buffer.

8. The method according to claim 1 wherein the logically erased physical blocks comprise all logically erased physical blocks of the non-volatile memory module.

9. The method according to claim 1 wherein the logically erased physical blocks form only a part of all logically erased physical blocks of the non-volatile memory module.

10. The method according to claim 1 comprising allocating the logically erased physical blocks to multiple spare block pools, wherein different spare block pools are associated with different types of programming, wherein different types of programming differ from each other by a number of logical bits programmed per flash memory cell;

and allocating, by the memory controller, physical blocks from the multiple spare block pools to become buffer blocks of the buffer of the non-volatile memory module.

11. The method according to claim 10 wherein the allocating of the physical blocks from the multiple spare block pools comprising independently managing the multiple spare block pools.

12. The method according to claim 1 further comprising allocating, by the memory controller, physical blocks that have become buffer blocks of a buffer of the non-volatile memory module to a sequential portion of the non-volatile memory module.

13. The method according to claim 1 further comprising allocating, by the memory controller, physical blocks from the spare block pool to a sequential portion of the non-volatile memory module.

14. A non-transitory computer readable medium that stores instructions that once executed by a memory controller cause the memory controller to:

allocate logically erased physical blocks of a non-volatile memory module to a spare block pool;

allocate physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and

control a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.

15. The non-transitory computer readable medium according to claim 14 that stores instructions that once executed by a memory controller cause the memory controller to initially allocate a predefined number of physical blocks to the spare block pool;

and further allocate to the spare block pool additional logically erased physical blocks.

16. The non-transitory computer readable medium according to claim 14 that stores instructions that once executed by a memory controller cause the memory controller to control cleaning operations in response to a status of the buffer.

17. The non-transitory computer readable medium according to claim 14 that stores instructions that once executed by a memory controller cause the memory controller to control a utilization of a memory section of the non-volatile memory module that differs from the buffer by applying a block based buffer management scheme.

18. The non-transitory computer readable medium according to claim 17 that stores instructions that once executed by a memory controller cause the memory controller to manage a logical block to physical block mapping data structure that maps logical blocks to mapped physical blocks.

19. The non-transitory computer readable medium according to claim 14 that stores instructions that once executed by a memory controller cause the memory controller to receive data sectors to be written to the non-volatile memory module and determine whether to write the data sectors to the buffer or to a mapped physical block.

20. The non-transitory computer readable medium according to claim 19 that stores instructions that once executed by a memory controller cause the memory controller to determine in response to a state of the buffer.

21. A memory controller, comprising:

an allocation circuit that is arranged to allocate logically erased physical blocks of a non-volatile memory module to a spare block pool and to allocate physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and

a buffer memory controller that is arranged to control a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.

22. The memory controller according to claim 21 wherein the allocation circuit is arranged to initially allocate a predefined number of physical blocks to the spare block pool;

and further allocate to the spare block pool additional logically erased physical blocks.

23. The memory controller according to claim 21 wherein the buffer memory controller is arranged to control cleaning operations in response to a status of the buffer.

24. The memory controller according to claim 21 comprising a block control circuit that is arranged to control a utilization of a memory section of the non-volatile memory module that differs from the buffer by applying a block based buffer management scheme.

25. The memory controller according to claim 24 that is arranged to manage a logical block to physical block mapping data structure that maps logical blocks to mapped physical blocks.

26. The memory controller according to claim 24 comprising an interface that is arranged to receive data sectors to be written to the non-volatile memory module and wherein the memory controller is arranged to determine whether to write the data sectors to the buffer of to a mapped physical block.

27. The memory controller according to claim 26 wherein the determining is responsive to a state of the buffer.