Dynamic memory cache size adjustment in a memory device

• US 9,195,604 B2
• Filed: 10/09/2014
• Issued: 11/24/2015
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nemazie, Siamack, Tabrizi, Farshid, Iman, Berhanu, Shah, Ruchir, Benson, William E., George, Michael
• Primary Examiner(s): RUTZ, JARED IAN
• Assistant Examiner(s): Lillis, Brendan
• Application Number:
  US14/510,179
• Publication Number:
  US 20150026416A1
• Time in Patent Office: 411 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/224 Disk storage
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory

Abstract

Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Claims

1. A method of operating a memory device, the method comprising:

disabling dynamic adjustment of a physical size of a memory cache of the memory device in response to determining that a file system on the memory device does not support dynamic cache size adjustment; and

enabling the disabled dynamic adjustment of the physical size of the memory cache in response to receiving a command that allows for the dynamic adjustment of the physical size of the memory cache regardless of the file system on the memory device not supporting dynamic cache size adjustment.

2. The method of claim 1, wherein the command is a TRIM command.

3. The method of claim 1, wherein the command is part of a protocol that allows deletion of a range of logical block addresses.

4. The method of claim 1, wherein dynamic adjustment of the physical size of the memory cache comprises adjustment of the physical size of the memory cache based on a size of available memory space in the memory device.

5. The method of claim 4, wherein the available memory space is one of erased memory that is not targeted for use or unerased memory that stores data that is not valid.

6. The method of claim 4, wherein the physical size of the memory cache is a portion of the available memory space.

7. The method of claim 4, further comprising determining the available memory space after every write or erase operation.

8. A memory device comprising:

a memory cache;

control circuitry; and

a file system;

wherein the control circuitry is configured to disable dynamic adjustment of a physical size of the memory cache in response to determining that the file system does not support dynamic cache size adjustment; and

wherein the control circuitry is configured to enable the disabled dynamic adjustment of the physical size of the memory cache in response to the memory device receiving a command that allows for the dynamic adjustment of the physical size of the memory cache regardless of the file system not supporting dynamic cache size adjustment.

9. The memory device of claim 8, wherein the control circuitry is configured to enable dynamic memory cache size adjustment in response to determining that the file system does support dynamic cache size adjustment.

10. A memory device, comprising:

a memory cache;

control circuitry; and

a file system;

wherein the control circuitry is configured to disable dynamic adjustment of a physical size of the memory cache in response to determining that the file system does not support dynamic cache size adjustment;

wherein the memory device supports a command protocol that allows for the dynamic adjustment of the physical size of the memory cache regardless of the file system not supporting dynamic cache size adjustment; and

wherein the control circuitry is configured to enable the disabled dynamic adjustment of the physical size of the memory cache in response to the memory device receiving a command of the command protocol.

11. The memory device of claim 10, wherein dynamic adjustment of the physical size of the memory cache comprises adjustment of the physical size of the memory cache based on a size of available memory space in the memory device.

12. The memory device of claim 11, wherein the available memory space in the memory device is variable.

13. The memory device of claim 10, wherein the command protocol that allows for the dynamic adjustment of the physical size of the memory cache allows deletion of ranges of logical block addresses.

14. The memory device of claim 10, wherein the command protocol that allows for the dynamic adjustment of the physical size of the memory cache is a TRIM protocol.

15. A memory system, comprising:

a memory device and a controller configured to implement a file system on the memory device, wherein the memory device comprises a memory cache;

wherein the controller is configured to disable dynamic adjustment of a physical size of the memory cache in response to determining that the file system does not support dynamic adjustment of the physical size of the memory cache; and

wherein the controller is further configured to enable the disabled dynamic adjustment of the physical size of the memory cache, regardless of the file system not supporting dynamic adjustment of the physical size of the memory cache, in response to determining that the memory device supports a command that allows for the dynamic adjustment of the physical size of the memory cache.

16. The memory system of claim 15, wherein the controller is configured to allocate different amounts of available memory space in the memory device to the memory cache when dynamic adjustment of the physical size of the memory cache is enabled.

17. The memory system of claim 15, wherein the controller is configured to use a step function to determine an amount of available memory space in the memory device to allocate to the memory cache when dynamic adjustment of the physical size of the memory cache is enabled.

18. The memory system of claim 15, wherein the controller is configured to use a linear function to determine an amount of available memory space in the memory device to allocate to the memory cache when dynamic adjustment of the physical size of the memory cache is enabled.

19. The memory system of claim 15, wherein the command is part of a protocol that allows deletion of a range of logical block addresses.

20. The memory system of claim 15, wherein the controller is configured to enable dynamic memory cache size adjustment in response to determining that the file system on the memory device does support dynamic cache size adjustment.