Liquid crystal display

• US 9,196,206 B2
• Filed: 04/22/2008
• Issued: 11/24/2015
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kitayama, Masae, Shimoshikiryoh, Fumikazu, Irie, Kentaroh, Tsubata, Toshihide, Yamada, Naoshi, Nakagawa, Hidetoshi
• Primary Examiner(s): XAVIER, ANTONIO J
• Application Number:
  US12/451,074
• Publication Number:
  US 20100097366A1
• Time in Patent Office: 2,772 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/122 having a particular pattern
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/2077 by a combination of two or more gradation control methods
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3666 : with the matrix divided into sections
• CPC Class Codes: G09G 3/3677 : suitable for active matrices only
• CPC Class Codes: G09G 3/3688 : suitable for active matrices only
• CPC Class Codes: G11C 19/00 : Digital stores in which the information is moved stepwise, e.g. shift registers

Abstract

In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the j^th scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)^th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.

Claims

1. A liquid crystal display device comprising:

a number of pixels that are arranged in columns and rows to form a matrix pattern, each said pixel including first and second subpixels that are able to exhibit mutually different luminances at least at a certain grayscale;

a plurality of source bus lines, each of which is connected with one of the columns of pixels;

a plurality of gate bus lines, each of which is connected with one of the rows of pixels;

a gate driver configured to supply gate signal voltages to the gate bus lines, respectively;

a source driver configured to supply source signal voltages to the source bus lines, respectively;

a controller;

a plurality of thin film transistors (TFTs), each of which is connected with one of the first and second subpixels of a connected one of the pixels; and

a plurality of storage capacitor (CS) bus lines, each of which is connected with either the respective first subpixels or the respective second subpixels of one of the rows of pixels, and

wherein each of the first and second subpixels includes a liquid crystal capacitor and a storage capacitor,

the liquid crystal capacitor of the first subpixel includes a first subpixel electrode and a counter electrode,

the liquid crystal capacitor of the second subpixel includes a second subpixel electrode and a counter electrode,

the counter electrode of the first liquid crystal capacitor and the counter electrode of the second liquid crystal capacitor are provided in common between the first subpixel and the second subpixel, and

a common voltage of the counter electrode does not substantially change its polarity within at least one vertical scanning period,

the CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other,

the gate driver is configured to scan the pixels by supplying the gate signal voltages to the respective gate bus,

the controller is configured to supply a CS voltage to each said CS bus line such that each CS voltage has a waveform, of which the polarity changes at least once a vertical scanning period,

the gate driver is configured to supply the gate signal voltages such that each said vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period,

the source driver is configured to supply the source signal voltages such that the polarity of the source signal voltage supplied to each said source bus line changes in a sequence which includes two vertical scanning periods or sub-periods, each of the two vertical scanning periods or sub-periods being defined by an opposite polarity of the source signal voltage, and

the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line has a waveform that alternately performs the function of increasing or decreasing the effective voltage of one of two subpixels, which is connected with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a jth gate bus line to be selected during the first vertical scanning sub-period, and the function of increasing or decreasing the effective voltage of one of two subpixels, which is connected with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a (j+1)th gate bus line to be selected during the second vertical scanning sub-period, wherein the source driver is configured to supply the source signal voltages such that the sequence of the source signal voltage to each source bus line includes a series of two vertical scanning periods in which the source signal voltage has mutually opposite polarities, the source signal voltage keeping the same polarity through the first and second vertical scanning sub-periods of the same vertical scanning period, and

wherein the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line inverts its polarity an odd number of times since a gate signal voltage supplied to the jth gate bus line has changed from high into low during the first vertical scanning sub-period and until a gate signal voltage supplied to the (j+1)th gate bus line changes from high into low during the second vertical scanning sub-period.

2. A liquid crystal display device comprising:

a number of pixels that are arranged in columns and rows to form a matrix pattern, each said pixel including first and second subpixels that are able to exhibit mutually different luminances at least at a certain grayscale;

a plurality of source bus lines, each of which is connected with one of the columns of pixels;

a plurality of gate bus lines, each of which is connected with one of the rows of pixels;

a gate driver configured to supply gate signal voltages to the gate bus lines, respectively;

a source driver configured to supply source signal voltages to the source bus lines, respectively;

a controller;

a plurality of thin film transistors (TFTs), each of which is connected with one of the first and second subpixels of a connected one of the pixels; and

a plurality of storage capacitor (CS) bus lines, each of which is connected with either the respective first subpixels or the respective second subpixels of one of the rows of pixels, and

wherein each of the first and second subpixels includes a liquid crystal capacitor and a storage capacitor,

the liquid crystal capacitor of the first subpixel includes a first subpixel electrode and a counter electrode,

the liquid crystal capacitor of the second subpixel includes a second subpixel electrode and a counter electrode,

the counter electrode of the first liquid crystal capacitor and the counter electrode of the second liquid crystal capacitor are provided in common between the first subpixel and the second subpixel, and

a common voltage of the counter electrode does not substantially change its polarity within at least one vertical scanning period,

the CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other,

the gate driver is configured to scan the pixels by supplying the gate signal voltages to the respective gate bus,

the controller is configured to supply a CS voltage to each said CS bus line such that each CS voltage has a waveform, of which the polarity changes at least once a vertical scanning period,

the gate driver is configured to supply the gate signal voltages such that each said vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period,

the source driver is configured to supply the source signal voltages such that the polarity of the source signal voltage supplied to each said source bus line changes in a sequence which includes two vertical scanning periods or sub-periods, each of the two vertical scanning periods or sub-periods being defined by an opposite polarity of the source signal voltage, and

the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line has a waveform that alternately performs the function of increasing or decreasing the effective voltage of one of two subpixels, which is connected with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a jth gate bus line to be selected during the first vertical scanning sub-period, and the function of increasing or decreasing the effective voltage of one of two subpixels, which is connected with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a (j+1)th gate bus line to be selected during the second vertical scanning sub-period, wherein the source driver is configured to supply the source signal voltages such that the sequence of the source signal voltage to each source bus line includes a series of two vertical scanning sub-periods in which the source signal voltage has mutually opposite polarities, the source signal voltage having mutually opposite polarities in the first and second vertical scanning sub-periods of the same vertical scanning period, and

wherein the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line inverts its polarity an even number of times since a gate signal voltage supplied to the jth gate bus line has changed from high into low during the first vertical scanning sub-period and until a gate signal voltage supplied to the (j+1)th gate bus line changes from high into low during the second vertical scanning sub-period.

3. The liquid crystal display device of claim 2, wherein the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line inverts its polarity an even number of times, which is at least twice, since the gate signal voltage supplied to the jth gate bus line has changed from high into low during the first vertical scanning sub-period and until the gate signal voltage supplied to the (j+1)th gate bus line changes from high into low during the second vertical scanning sub-period, and

wherein once a voltage has been applied to the (j+1)th row of pixels, the CS voltage level stays at the center level thereof.

4. The liquid crystal display device of claim 2, wherein the gate driver is configured to supply the gate signal voltages such that every odd or even row of pixels are scanned during the first vertical scanning sub-period and the rest of the odd or even rows of pixels that have not been scanned yet are scanned during the second vertical scanning sub-period.

5. The liquid crystal display device of claim 2, wherein the CS bus lines include at least one CS bus line that is connected in common with two subpixels that belong to two different pixels and that are adjacent to each other in the column direction.

6. The liquid crystal display device of claim 2, wherein the controller is configured to supply the CS voltages such that the CS voltage to each CS bus line has a waveform, a part of which oscillates in a period that is a positive integral number of times as long as one horizontal scanning period, and

wherein the gate driver is configured to supply the gate signal voltages such that each said vertical scanning sub-period is a period for scanning a series of Nsv (=α

/2) odd or even rows of pixels, a being a positive integral and a multiple of M, and

wherein if one period of the CS voltage is represented by M×

H where H is one horizontal scanning period and M is a positive integer, Nsv is a positive integral number of times as large as M/2.

7. The liquid crystal display device of claim 6, wherein the gate driver is configured to supply the gate signal voltages such that each said vertical scanning period includes not only the first and second vertical scanning sub-periods but also third and fourth vertical scanning sub-periods that are continuous with the second and third vertical scanning sub-periods, respectively, and

wherein the third vertical scanning sub-period is a period for sequentially scanning a series of Nsv odd or even rows of pixels, beginning with an odd or even row continuously with the last odd or even row that has been scanned during the second vertical scanning sub-period, while the fourth vertical scanning sub-period is a period for sequentially scanning even or odd rows of pixels that have been skipped during the third vertical scanning sub-period, and

wherein the sequence includes a sequence in which the source signal voltage has different polarities between the first and second vertical scanning sub-periods, the same polarity between the second and third vertical scanning sub-periods, and different polarities again between the third and fourth vertical scanning sub-periods.

8. The liquid crystal display device of claim 6, wherein the CS bus lines include at least one CS bus line that is connected in common with two subpixels that belong to two different pixels and that are adjacent to each other in the column direction, and

wherein the controller is configured to supply the CS voltages such that if one period of the CS voltage to each CS bus line is represented by M×

H where H is one horizontal scanning period and M is a positive integer, Nsv is a positive integral number of times as large as M.

9. The liquid crystal display device of claim 6, wherein Nsv×

H (where H is one horizontal scanning period) is equal to or shorter than 1.2 ms.

10. The liquid crystal display device of claim 6, wherein the gate driver is configured to supply the gate signal voltages the number of horizontal scanning periods included in one vertical scanning period is Nv-total and (Nsv/Nv-total)×

one vertical scanning period is equal to or shorter than 1.2 ms.

11. The liquid crystal display device of claim 6, wherein the gate driver is configured to supply the gate signal voltages such that if the number of horizontal scanning periods included in one effective display period is Nv-Disp, then Nv-Disp is an integral number of times as large as Nsv×

2.

12. The liquid crystal display device of claim 2, wherein the source driver is configured to supply the source signal voltages such that in an arbitrary vertical scanning period, source signal voltages supplied to two source bus lines that are connected with mutually adjacent columns of pixels have opposite polarities.

13. The liquid crystal display device of claim 2, wherein one vertical scanning sub-period is equal or shorter than 1/120 second.

14. A TV receiver comprising:

the liquid crystal display device of claim 2; and

a tuner, which receives a TV broadcast and outputs a video signal to the liquid crystal display device.