Semiconductor storage device

• US 9,196,375 B2
• Filed: 11/20/2013
• Issued: 11/24/2015
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kumazaki, Noriyasu, Yoshihara, Masahiro
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/084,898
• Publication Number:
  US 20150009763A1
• Time in Patent Office: 734 Days
• Field of Search: 365/63, 365/51, 365/226, 365/189.08
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path of the memory cells. A sense amplifier part detects data stored in the selected memory cells. A power supply part converts an external power supply voltage to an internal power supply voltage and supplies the internal power supply voltage to the sense amplifier part. A power supply wire extends above the memory cell array and is provided to range from the power supply part to the sense amplifier part.

Claims

1. A semiconductor storage device comprising:

a memory cell array comprising a plurality of memory cells;

a plurality of word lines electrically connected to control gates of the memory cells;

a plurality of bit lines electrically connected to one end of a current path of the memory cells;

a sense amplifier part configured to detect data stored in the selected memory cells;

a power supply part configured to convert an external power supply voltage to an internal power supply voltage and to supply the internal power supply voltage to the sense amplifier part, the memory cell array being disposed between the sense amplifier and the power supply part;

a power supply wire extending above a first area in the memory cell array, the first area being between the power supply part and the sense amplifier part; and

a discharge part electrically connected to the power supply wire and configured to discharge the power supply wire when a voltage of the power supply wire exceeds a first voltage.

2. The device of claim 1, wherein the first voltage is the internal power supply voltage.

3. The device of claim 1, wherein

the discharge part comprises a clamp transistor provided between the power supply wire and a second voltage, and

a gate voltage of a gate of the clamp-type transistor is capable of setting to a third voltage.

4. The device of claim 2, wherein

the discharge part comprises a clamp transistor provided between the power supply wire and a second voltage, and

a gate voltage of a gate of the clamp-type transistor is capable of setting to a third voltage.

5. The device of claim 3, wherein the gate voltage of the clamp transistor is capable of setting to a voltage obtained by subtracting a threshold voltage of the clamp transistor from the internal power supply voltage.

6. The device of claim 4, wherein the gate voltage of the clamp transistor is capable of setting to a voltage obtained by subtracting a threshold voltage of the clamp transistor from the internal power supply voltage.

7. The device of claim 5, further comprising a gate voltage generator comprising a first transistor smaller in a size than the clamp transistor, the first transistor being substantially equal in a threshold voltage to the clamp transistor, and the gate voltage generator configured to generate a gate voltage of the clamp transistor using the first transistor.

8. The device of claim 6, further comprising a gate voltage generator comprising a first transistor smaller in a size than the clamp transistor, the first transistor being substantially equal in a threshold voltage to the clamp transistor, and the gate voltage generator configured to generate a gate voltage of the clamp transistor using the first transistor.

9. The device of claim 1, wherein the discharge part is commonly provided to a plurality of the power supply wires or a plurality of the power supply parts.

10. The device of claim 2, wherein the discharge part is commonly provided to a plurality of the power supply wires or a plurality of the power supply parts.

11. A semiconductor storage device comprising:

a memory cell array comprising a plurality of memory cells;

a plurality of word lines electrically connected to control gates of the memory cells;

a plurality of bit lines electrically connected to one end of a current path of the memory cells;

a sense amplifier part configured to detect data stored in the selected memory cells;

a power supply part configured to convert an external power supply voltage to an internal power supply voltage and to supply the internal power supply voltage to the sense amplifier part, the memory cell array being disposed between the sense amplifier and the power supply part;

a power supply wire extending above a first area in the memory cell array, the first area being between the power supply part and the sense amplifier part; and

a discharge part electrically connected to the power supply wire and configured to discharge the power supply wire when a voltage of the power supply wire exceeds a first voltage.

12. The device of claim 11, wherein the power supply wire extends above the memory cell array.

13. The device of claim 11, wherein the first voltage is the internal power supply voltage.

14. The device of claim 11, wherein

the discharge part comprises a clamp transistor provided between the power supply wire and a second voltage, and

a gate voltage of a gate of the clamp-type transistor is capable of setting to a third voltage.

15. The device of claim 14, wherein the gate voltage of the clamp transistor is capable of setting to a voltage obtained by subtracting a threshold voltage of the clamp transistor from the internal power supply voltage.

16. The device of claim 14, further comprising a gate voltage generator comprising a first transistor smaller in a size than the clamp transistor, the first transistor being substantially equal in a threshold voltage to the clamp transistor, and the gate voltage generator configured to generate a gate voltage of the clamp transistor using the first transistor.

17. The device of claim 15, further comprising a gate voltage generator comprising a first transistor smaller in a size than the clamp transistor, the first transistor being substantially equal in a threshold voltage to the clamp transistor, and the gate voltage generator configured to generate a gate voltage of the clamp transistor using the first transistor.

18. The device of claim 11, wherein the discharge part is commonly provided to a plurality of the power supply wires or a plurality of the power supply parts.