Semiconductor device and method

• US 9,196,477 B2
• Filed: 04/03/2012
• Issued: 11/24/2015
• Est. Priority Date: 04/05/2011
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Cheng, Kai, Caymax, Matty
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): NGUYEN, LAWRENCE-LIN T
• Application Number:
  US13/438,718
• Publication Number:
  US 20130001507A1
• Time in Patent Office: 1,330 Days
• Field of Search: 257/9, 257 79-103, 257/618, 257/E21.9, 257/E29.2, 257/E29.24
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Abstract

A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

providing a first epitaxial semiconducting layer over the substrate; and

forming a periodic pattern in the first epitaxial semiconducting layer after providing the first epitaxial semiconducting layer, the periodic pattern comprising a plurality of recessed portions, the recessed portions periodically repeating in at least one direction parallel to a surface of the first epitaxial semiconducting layer, wherein the recessed portions have an aspect ratio between a depth and a lateral dimension in the at least one direction in the range of about 0.1 to 50.

2. The method according to claim 1, further comprising, subsequent to forming the periodic pattern, providing a second epitaxial semiconducting layer over the first epitaxial semiconducting layer.

3. The method according to claim 1, wherein the recessed portions have the lateral dimension in the range of about 0.5 to 5 μ

m.

4. The method according to claim 1, wherein the recessed portions have a depth in the range of about 0.2 to 2 μ

m.

5. The method according to claim 1, wherein the pattern comprises repeating structures having a shape selected from one or more of a trench, a pit, a slit, a pillar, a pyramid, a square, a rectangle, a hexagon, a multigon, a circle, and an ellipse.

6. The method according to claim 1, further comprising forming a buffer layer on the substrate before forming the first epitaxial semiconducting layer, wherein the buffer layer comprises one or more of:

an initial layer formed on the substrate; and

a second layer forming a buffer comprising AlGaN, wherein the Al content decreases from bottom to top.

7. The method according to claim 1, wherein two or more first III-V epitaxial semiconducting layers are provided, and/or wherein two or more second III-V epitaxial semiconducting layers are provided.

8. The method according to claim 7, wherein the two or more first III-V epitaxial semiconducting layers are two or more further III-V layers form a stack of alternating III-V layers of two or more types, wherein the stack provides a multiple quantum well.

9. A semiconductor device as manufactured according to the method of claim 1.

10. A high current low carrier density semiconductor device having a high break down voltage, the device comprising:

a substrate;

a first epitaxial semiconducting layer formed over the substrate; and

a periodic pattern in the first epitaxial semiconducting layer, the periodic pattern comprising recessed portions, the recessed portions periodically repeating in at least one direction parallel to a surface of the first epitaxial semiconducting layer, the surface on an opposite side to the substrate, wherein the recessed portions have an aspect ratio between a depth and a lateral dimension in the at least one direction in the range of about 0.1 to 50.

11. The device according to claim 10, the device further comprising a second epitaxial semiconducting layer formed over the first epitaxial semiconducting layer.

12. The device according to claim 10, wherein the recessed portions have the lateral dimension in the range of about 0.5 to 5 μ

m.

13. The device according to claim 10, wherein the recessed portions have a depth in the range of about 0.2 to 2 μ

.

14. The device according to claim 10, wherein the pattern comprises repeating structures having a shape selected from one or more of a trench, a pit, a slit, a pillar, a pyramid, a square, a rectangle, a hexagon, a multigon, a circle, and an ellipse.

15. An electronic circuit comprising a semiconductor device according to claim 10.

16. The electronic circuit according to claim 15, the electronic circuit being a transistor, a FET, a HEMT, a DHFET, a LED, a diode, or a power device.

17. An apparatus comprising a semiconductor device according to claim 10, the apparatus being an electronic circuit, a switch, a high power application, a high voltage application, an image sensor, a biosensor, or an ion sensor.

18. A method of manufacturing a semiconductor device, the method comprising:

providing a silicon substrate;

forming a periodic pattern in the silicon substrate, the periodic pattern comprising a plurality of recessed portions, the recessed portions periodically repeating in at least one direction parallel to a surface of the silicon substrate, wherein the recessed portions have an aspect ratio between a depth and a lateral dimension in the at least one direction in the range of about 0.1 to 50; and

providing a first epitaxial semiconducting layer on the substrate.

19. The method of claim 18, wherein the surface of the silicon substrate has a {111} crystal plane and the recessed portions include trenches extending in a <

110>

direction.

20. A high current low carrier density semiconductor device having a high break down voltage, the device comprising:

a silicon substrate;

a periodic pattern formed in the silicon substrate, the periodic pattern comprising a plurality of recessed portions, the recessed portions periodically repeating in at least one direction parallel to the surface, wherein the recessed portions have an aspect ratio between a depth and a lateral dimension in the at least one direction in the range of about 0.1 to 50; and

a first epitaxial semiconducting layer formed on the silicon substrate.

21. The method of claim 20, wherein the surface of the silicon substrate has a {111} crystal plane and the recessed portions include trenches extending in a <

110>

direction.