Semiconductor device and manufacturing method having copper interconnects with metal film, barrier metal, and metal caps

• US 9,196,526 B2
• Filed: 11/12/2013
• Issued: 11/24/2015
• Est. Priority Date: 03/18/2013
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kanki, Tsuyoshi
• Primary Examiner(s): Parendo, Kevin
• Assistant Examiner(s): KOO, LAMONT B
• Application Number:
  US14/078,139
• Publication Number:
  US 20140264875A1
• Time in Patent Office: 742 Days
• Field of Search: 257/751, 438/653
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film.

Claims

1. A semiconductor device comprising:

a copper interconnect provided in a damascene trench in an insulation film;

a metal film provided on the insulation film along a boundary between a top face of the insulation film and an uppermost part of the copper interconnect;

a barrier metal provided between an inner wall of the damascene trench and the copper interconnect and extending over the metal film;

a first metal cap covering a top face of the copper interconnect and a top face of the barrier metal located over the metal film, the first metal cap having overflowed from the top face of the copper interconnect to the top face of the barrier metal located over the metal film; and

a second metal cap directly covering a top surface of the first metal cap, an end face of the barrier metal, and an end face of the metal film, the second metal cap being in contact with the top surface of the first metal cap, the end face of the barrier metal, and the end face of the metal film.

2. The semiconductor device according to claim 1, wherein the metal film is a residual of a metal mask used to form the damascene trench in the insulation film.

3. The semiconductor device according to claim 1, wherein the metal film, the barrier metal, the first metal cap and the second metal cap are layered in this order on the insulation film along the boundary between the copper interconnect and the insulation film, and the second metal cap continuously covers an end face of the first metal cap, the end face of the barrier metal, and the end face of the metal film.

4. The semiconductor device according to claim 1, wherein the metal film is formed of a material different from the barrier metal.

5. The semiconductor device according to claim 1, wherein the metal film is formed of a material that allows the second metal cap to be deposited.

6. The semiconductor device according to claim 1, wherein a material of the metal film is selected from Co, Ni, Cr, Fe, Pt, or Au.

7. The semiconductor device according to claim 1, wherein a material of the second metal cap is selected from Co, Ni, W—

P, Ni—

P, Ni—

W—

P, Co—

W—

P, or Au.

8. The semiconductor device according to claim 1, wherein the copper interconnect is a rewiring interconnect formed on a substrate on which a semiconductor chip is mounted.

9. The semiconductor device according to claim 1, wherein the copper interconnect is a global interconnect formed in a semiconductor chip.