Method for manufacturing semiconductor devices

• US 9,196,542 B2
• Filed: 05/22/2013
• Issued: 11/24/2015
• Est. Priority Date: 05/22/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Jun-Jie, Tsao, Po-Chao, Liang, Chia-Jui, Tzou, Shih-Fang, Lin, Chien-Ting
• Primary Examiner(s): MULPURI, SAVITRI
• Application Number:
  US13/899,581
• Publication Number:
  US 20140349452A1
• Time in Patent Office: 916 Days
• Field of Search: 438/238
• US Class Current: 1/1
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

Claims

1. A method for manufacturing a semiconductor device, wherein the semiconductor device has a transistor region and a resistor region, the method comprising:

forming a first fin structure and a second fin structure on a substrate, wherein the first fin structure and the second fin structure are in the transistor region and the resistor region respectively;

forming a first stack structure and a second stack structure so as to respectively cover a portion of the first fin structure and of the second fin structure, wherein the first stack structure and the second stack structure respectively include a dummy layer and a hard mask layer from bottom to top;

forming a spacer respectively on sidewalls of the first stack structure and of the second stack structure through an atomic layer deposition process, wherein a composition of the spacers includes silicon carbon nitride;

forming an interlayer dielectric covering the first stack structure, the second stack structure and the spacers;

etching the interlayer dielectric so as to expose each of the hard mask layers;

forming a mask layer to cover the second stack structure and a portion of the dielectric layer;

removing the hard mask layer in the first stack structure under a coverage of the mask layer, wherein after the hard mask layer is removed, the height of the spacer is same as the height of the spacer before the hard mask layer is removed;

removing the dummy layer in the first stack structure to leave a first trench;

forming a high-k dielectric layer above sidewalls and a bottom of the first trench;

forming a work function metal layer on the high-k dielectric layer; and

filling up the first trench with a conductive layer after forming the work function metal layer on the high-k dielectric layer.

2. The method according to claim 1, wherein a composition of the hard mask layers includes silicon nitride.

3. The method according to claim 1, wherein each of the spacers is a single-layered spacer or a double-layered spacer.

4. The method according to claim 1, wherein a process for etching the dielectric layer is an etching back process.

5. The method according to claim 4, wherein the etching back process is a dry etching process.

6. The method according to claim 1, wherein a composition of the mask layer is polymer.

7. The method according to claim 1, wherein both the first stack structure and the second stack structure have a first height before etching the interlayer dielectric.

8. The method according to claim 7, wherein the first stack structure and the second stack structure have a second height after etching the interlayer dielectric, wherein the second height is lower than the first height.

9. The method according to claim 8, wherein the second stack structure has the second height after removing the hard mask layer in the first stack structure.

10. The method according to claim 1, wherein a process for removing the hard mask layer in the first stack structure is a selective etching process.

11. The method according to claim 10, wherein the selective etching process is a wet etching process.

12. The method according to claim 1, wherein the dummy layer in the first stack structure is exposed after removing the hard mask layer in the first stack structure.

13. The method according to claim 1, further comprising forming a contact etch stop layer, wherein the contact etch stop layer is disposed between the spacers and the dielectric layer.

14. The method according to claim 13, wherein a composition of the contact etch stop layer includes silicon carbon nitride.

15. The method according to claim 1, further comprising forming an epitaxial layer on the first fin structure and at a side of the first stack structure.