Structure and method for finFET device

• US 9,196,543 B2
• Filed: 02/27/2015
• Issued: 11/24/2015
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US14/633,748
• Publication Number:
  US 20150235905A1
• Time in Patent Office: 270 Days
• Field of Search: 438/238, 257/E27.06
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A method of forming a fin field effect transistor (FinFET) structure including forming a plurality of shallow trench isolation (STI) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the STI features. The method then forms a first hard mask layer on the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas. A second semiconductor material is then grown on the semiconductor substrate within the plurality of openings of the first hard mask layer, thereby forming a multi-fin active region having multiple fin features within the one of the bulk-semiconductor areas.

Claims

1. A method of forming a fin field effect transistor (FinFET) structure, the method comprising:

forming a plurality of shallow trench isolation (STI) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the STI features;

forming a first hard mask layer over the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas; and

epitaxially growing a semiconductor material within the plurality of openings defined by the first hard mask layer, thereby forming a multi-fin active region having multiple fin features within the one of the bulk-semiconductor areas.

2. The method of claim 1, further comprising:

performing a chemical mechanical polishing (CMP) process on the semiconductor material after the epitaxial growth; and

thereafter removing the first hard mask layer.

3. The method of claim 2, wherein:

the semiconductor substrate includes a first semiconductor material is silicon; and

the epitaxially grown semiconductor material is a second semiconductor material different from the first semiconductor material.

4. The method of claim 1, further comprising:

forming a dielectric material layer over the semiconductor substrate;

patterning the dielectric material layer to form a plurality of dielectric mesas on the semiconductor substrate;

forming spacer features on sidewalls of the dielectric mesas; and

removing the dielectric mesas, wherein the spacer features define the pattern of the first hard mask layer.

5. The method of claim 4, further comprising performing a reverse-tone process that includes:

forming a material layer on the semiconductor substrate and within openings defined by the spacer features; and

removing the spacer features.

6. The method of claim 5, where the forming of the material layer includes:

forming the material layer by spin coating; and

selectively etching back the material layer to expose the spacer features.

7. The method of claim 5, where the forming of the material layer includes:

forming the material layer by deposition process; and

performing a polishing process to the material layer to expose the spacer features.

8. The method of claim 1, further comprising:

forming a first dielectric layer on the semiconductor substrate and a second dielectric layer on the first dielectric layer, prior to the forming of the first hard mask layer; and

wherein the epitaxially growing of the semiconductor material includes growing the semiconductor material within openings of the first and second dielectric layers.

9. A method, comprising:

providing shallow trench isolation (STI) features formed in a semiconductor substrate, wherein the STI features define a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and

forming a first and second fin features disposed on one of the semiconductor regions of the semiconductor substrate, wherein forming the first and second fin includes forming the first and second fin such that a bottom region of each of the first and second fin features is substantially coplanar with a top surface of the semiconductor region interposing the first and second fin features.

10. The method of claim 9, wherein the forming the first and second fin features includes epitaxially growing the first and second fin features.

11. The method of claim 9, wherein the forming the first and second fin features further includes:

forming a hard mask layer over the semiconductor region;

patterning the hard mask layer to form a first opening and a second opening; and

epitaxially growing the first and second fin features in the first opening and second opening respectively.

12. The method of claim 9, wherein the forming the first and second fin features includes:

forming a first layer over the semiconductor region;

forming a second layer over the first layer;

patterning the second layer to form a plurality of features;

forming spacer elements on sidewalls of each of the plurality of features; and

after forming the spacer elements, removing the plurality of features from the semiconductor substrate.

13. The method of claim 12, wherein the forming the first and second fin features further includes:

depositing a third layer over the spacer elements; and

after depositing the third layer removing the spacer elements to form a first and a second opening in the third layer, wherein each of the first and second opening have a width defined by one of the spacer elements; and

etching the first layer using the first and second openings to define third and fourth openings in the first layer.

14. The method of claim 13, wherein the forming the first and second fin features further includes:

epitaxially growing the first fin from the one of the semiconductor regions such that the first fin fills the third opening; and

epitaxially growing the second fin from the one of the semiconductor regions such that the second fin fills the fourth opening.

15. The method of claim 9, wherein the forming the first and second fin features includes forming non-rectangular fin features.

16. A method, comprising:

forming a shallow trench isolation (STI) features in a semiconductor substrate, wherein the STI features have a substantially coplanar top surface with a top surface of a region of the semiconductor substrate interposing the STI features;

forming a first and second fin features disposed over the top surface of the region of the semiconductor substrate interposing the STI features.

17. The method of claim 16, further comprising:

forming a gate over the first fin feature;

forming a channel region in the first fin feature interfacing the gate.

18. The method of claim 17, wherein the forming the first fin includes forming two opposing sidewalls of the channel region of the first fin that have an inner intersecting angle with respect to the top surface of the region of the semiconductor substrate, the inner intersecting angle being greater than 90 degrees.

19. The method of claim 16, wherein the forming the first and second fins includes epitaxially growing the first and second fins.

20. The method of claim 19, wherein the region of the semiconductor substrate includes a first semiconductor material and the epitaxially growing the first and second fins includes epitaxially growing a second semiconductor material, different than the first semiconductor material.