Dual shallow trench isolation and related applications
First Claim
1. A method comprising:
- providing a substrate having a pixel area and a periphery area;
providing a mask over the substrate;
photo patterning for a first STI structure in the pixel area and a second STI structure in the periphery area;
etching the mask and the substrate to form the first STI structure and the second STI structure having a first depth;
protecting the pixel area;
etching the second STI structure to a second depth deeper than the first depth;
forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and
forming second NMOS devices and PMOS devices in the periphery area.
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Accused Products
Abstract
Embodiments of the invention relate to dual shallow trench isolations (STI). In various embodiments related to CMOS Image Sensor (CIS) technologies, the dual STI refers to one STI structure in the pixel region and another STI structure in the periphery or logic region. The depth of each STI structure depends on the need and/or isolation tolerance of devices in each region. In an embodiment, the pixel region uses NMOS devices and the STI in this region is shallower than that of in the periphery region that includes both NMOS and PMOS device having different P- and N-wells and that desire more protective isolation (i.e., deeper STI). Depending on implementations, different numbers of masks (e.g., two, three) are used to generate the dual STI, and are disclosed in various method embodiments.
10 Citations
19 Claims
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1. A method comprising:
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providing a substrate having a pixel area and a periphery area; providing a mask over the substrate; photo patterning for a first STI structure in the pixel area and a second STI structure in the periphery area; etching the mask and the substrate to form the first STI structure and the second STI structure having a first depth; protecting the pixel area; etching the second STI structure to a second depth deeper than the first depth; forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and forming second NMOS devices and PMOS devices in the periphery area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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forming a first masking layer over a substrate, the substrate having a pixel area and a periphery area; etching the first masking layer and the substrate to form a first opening and a second opening in the pixel area and a third opening in the periphery area, the first, second, and third openings having a first depth; forming a second masking layer covering the pixel area; etching, using the first and second masking layers as a mask, the substrate to extend the third opening to a second depth deeper than the first depth; forming a first shallow trench isolation (STI) structure in the first opening, a second STI structure in the second opening, and a third STI structure in the third opening; forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices, the at least one photo detector being positioned between the first STI structure and the second STI structure; and forming second NMOS devices and PMOS devices in the periphery area. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification