Semiconductor package with single sided substrate design and manufacturing methods thereof

• US 9,196,597 B2
• Filed: 08/06/2014
• Issued: 11/24/2015
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Su, Yuan-Chang, Huang, Shih-Fu, Chen, Chia-Cheng, Chen, Tzu-Hui, Chen, Kuang-Hsiung, Hsieh, Pao-Ming, Lee, Ming Chiang, Appelt, Bernd Karl
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US14/453,139
• Publication Number:
  US 20140346670A1
• Time in Patent Office: 475 Days
• Field of Search: 257/700, 257/701, 257/778, 257/698
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/28 : Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/296 : Organo-silicon compounds
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Claims

1. A semiconductor package, comprising:

a substrate including;

a first patterned conductive layer having an upper surface;

a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a portion of the first patterned conductive layer to form a plurality of first contact pads;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein;

the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;

a die electrically connected to the plurality of first contact pads; and

a package body covering the first dielectric layer and the die;

wherein at least one of the plurality of conductive posts has an upper surface having a first area and a lower surface having a second area, and the first area is larger than the second area.

2. A semiconductor package, comprising:

a substrate including;

a first patterned conductive layer having an upper surface;

a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a portion of the first patterned conductive layer to form a plurality of first contact pads;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein;

the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;

a die electrically connected to the plurality of first contact pads; and

a package body covering the first dielectric layer and the die;

wherein the first patterned conductive layer includes a first conductive layer, a second conductive layer, and a seed layer therebetween.

3. A substrate, comprising:

a patterned conductive layer having an upper surface and a lower surface;

a first dielectric layer disposed adjacent to the upper surface of the patterned conductive layer, the first dielectric layer exposing a portion of the patterned conductive layer to form a plurality of contact pads;

a second dielectric layer disposed adjacent to the lower surface of the patterned conductive layer, wherein the second dielectric layer defines a plurality of openings; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the patterned conductive layer and through a corresponding one of the plurality of openings in the second dielectric layer, wherein both of the first dielectric layer and the second dielectric layer are unreinforced material.

4. The substrate of claim 3,

wherein the second dielectric layer includes a lower surface;

and

a carrier is disposed adjacent to the lower surface of the second dielectric layer.

5. The substrate of claim 4, wherein the carrier includes a support member and a conductive sheet, and the conductive sheet is between the support member and the lower surface of the second dielectric layer.

6. The substrate of claim 3, wherein the patterned conductive layer includes a first conductive layer, a second conductive layer, and a seed layer therebetween.

7. The substrate of claim 3, wherein the patterned conductive layer and the conductive post are formed integrally.

8. A semiconductor package, comprising:

a substrate including;

a patterned conductive layer having an upper surface and a lower surface;

a first dielectric layer disposed adjacent to the upper surface of the patterned conductive layer, the first dielectric layer exposing a portion of the patterned conductive layer to form a plurality of contact pads;

a second dielectric layer disposed adjacent to the lower surface of the patterned conductive layer, wherein;

the second dielectric layer defines a plurality of openings; and

a plurality of conductive posts, each of the plurality of conductive posts protruding from the patterned conductive layer and through a corresponding one of the plurality of openings in the second dielectric layer, wherein both of the first dielectric layer and the second dielectric layer are unreinforced material;

a die electrically connected to the plurality of contact pads; and

a package body covering the first dielectric layer and the die.

9. The semiconductor package of claim 8, wherein the patterned conductive layer includes a first conductive layer, a second conductive layer, and a seed layer therebetween.

10. The semiconductor package of claim 8, wherein the patterned conductive layer and the conductive post are formed integrally.

11. A semiconductor package, comprising:

a substrate including;

a first patterned conductive layer including a plurality of first contact pads and at least a first trace;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a first dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein;

the first dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads and at least a second trace;

a second dielectric layer disposed on the first dielectric layer, the second dielectric layer exposing the first contact pads and covering the first trace; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the first dielectric layer;

a die electrically connected to the plurality of first contact pads; and

a package body covering the die.

12. The semiconductor package of claim 11, wherein:

the first dielectric layer has a lower surface; and

the lower surface of the second patterned conductive layer is recessed from the lower surface of the first dielectric layer.

13. The semiconductor package of claim 11, further comprising:

a third dielectric layer disposed on the first dielectric layer, the third dielectric layer exposing the second contact pads.

14. The semiconductor package of claim 11, wherein at least one of the plurality of conductive posts has an upper surface having a first area and a lower surface having a second area, and the first area is different than the second area.

15. A substrate comprising:

a first patterned conductive layer including a plurality of first contact pads and at least a first trace;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a first dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein;

the first dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads and at least a second trace;

a second dielectric layer disposed on the first dielectric layer, the second dielectric layer exposing the first contact pads and covering the first trace; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the first dielectric layer.

16. The substrate of claim 15 wherein:

the first dielectric layer has a lower surface; and

the lower surface of the second patterned conductive layer is recessed from the lower surface of the first dielectric layer.

17. The substrate of claim 15, further comprising:

a third dielectric layer disposed on the first dielectric layer, the third dielectric layer exposing the second contact pads.

18. The substrate of claim 15, wherein at least one of the plurality of conductive posts has an upper surface having a first area and a lower surface having a second area, and the first area is different than the second area.