Array substrate with a gate driver on array (GOA) circuit and display device

• US 9,196,640 B2
• Filed: 12/23/2013
• Issued: 11/24/2015
• Est. Priority Date: 12/24/2012
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Xu, Chao, Kim, Heecheol
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US14/139,834
• Publication Number:
  US 20140175446A1
• Time in Patent Office: 701 Days
• Field of Search: 257/71, 257/59, 257/88, 257/98, 257/100, 257/43, 438/155, 438/149, 438/34
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode.

Claims

1. An array substrate including a gate driver on array (GOA) circuit area which includes a thin film transistor (TFT) area for outputting a gate row-driving signal and a lead-wire area connected to the TFT area, and a display area which includes a data line and a gate line which are arranged crosswise;

wherein

the GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via;

the GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode of the first electrode and the second electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode of the first electrode and the second electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode, wherein

the first electrode is connected to a pixel electrode, and the second electrode is connected to a common electrode;

or

the first electrode is connected to a common electrode, and the second electrode is connected to a pixel electrode.

2. The array substrate according to claim 1, wherein the display area is further provided with a first transparent electrode and a second transparent electrode, the first transparent electrode and the first electrode are formed in the same layer by a single patterning process, and the second transparent electrode and the second electrode are formed in the same layer by using a single patterning process.

3. The array substrate according to claim 1, wherein the lead-wire area further includes:

a third electrode integrally formed with the first electrode and a fourth electrode integrally formed with the second electrode, and a capacitor is formed between the third electrode and the fourth electrode.

4. The array substrate according to claim 1, wherein the TFT area further includes:

a gate-insulating layer and a semiconductor active layer which are between the gate-line metal layer and the data-line metal layer;

a resin layer between the data-line metal layer and the first electrode; and

a passivation layer between the first electrode and the second electrode.

5. The array substrate according to claim 4, wherein

the at least one first via penetrates through the resin layer to expose the data-line metal layer, and the at least one second via penetrates through the passivation layer, the resin layer, and the gate-insulating layer to expose the gate-line metal layer;

or the at least one first via penetrates through the passivation layer and the resin layer to expose the data-line metal layer, and the at least one second via penetrates through the resin layer and the gate-insulating layer to expose the gate-line metal layer.

6. A display device including an array substrate, the array substrate includes a gate driver on array (GOA) circuit area which includes a thin film transistor (TFT) area for outputting a gate row-driving signal and a lead-wire area connected to the TFT area, and a display area which includes a data line and a gate line which are arranged crosswise;

wherein

the GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via;

the GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode of the first electrode and the second electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode of the first electrode and the second electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode, wherein

the first electrode is connected to a pixel electrode, and the second electrode is connected to a common electrode;

or

the first electrode is connected to a common electrode, and the second electrode is connected to a pixel electrode.

7. The display device according to claim 6, wherein the display area is further provided with a first transparent electrode and a second transparent electrode, the first transparent electrode and the first electrode are formed in the same layer by a single patterning process, and the second transparent electrode and the second electrode are formed in the same layer by using a single patterning process.

8. The display device according to claim 6, wherein the lead-wire area further includes:

a third electrode integrally formed with the first electrode and a fourth electrode integrally formed with the second electrode, and a capacitor is formed between the third electrode and the fourth electrode.

9. The display device according to claim 6, wherein the TFT area further includes:

a gate-insulating layer and a semiconductor active layer which are between the gate-line metal layer and the data-line metal layer;

a resin layer between the data-line metal layer and the first electrode; and

a passivation layer between the first electrode and the second electrode.

10. The display device according to claim 9, wherein

the at least one first via penetrates through the resin layer to expose the data-line metal layer, and the at least one second via penetrates through the passivation layer, the resin layer, and the gate-insulating layer to expose the gate-line metal layer;

or the at least one first via penetrates through the passivation layer and the resin layer to expose the data-line metal layer, and the at least one second via penetrates through the resin layer and the gate-insulating layer to expose the gate-line metal layer.