Through substrate features in semiconductor substrates

• US 9,196,670 B2
• Filed: 02/13/2014
• Issued: 11/24/2015
• Est. Priority Date: 09/25/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mackh, Gunther, Leuschner, Rainer, Siedel, Uwe
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US14/180,188
• Publication Number:
  US 20140159196A1
• Time in Patent Office: 649 Days
• Field of Search: 257/277, 257/531, 257/774, 257/E21.022, 257/E23.011, 257/E23.067, 257/E23.145, 257/E23.175, 257/E21.585, 257/E29.166, 438/381, 438/667, 438/668
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a through substrate via disposed in a first region of a semiconductor substrate;

a through substrate conductor coil disposed in a second region of the semiconductor substrate;

an insulating liner disposed on sidewall of the through substrate via; and

a sidewall insulating liner disposed on the sidewall of the semiconductor device, the sidewall insulating liner covering a sidewall of the semiconductor substrate, wherein the insulating liner and the sidewall insulating liner comprise the same material.

2. The device of claim 1, wherein the through substrate conductor coil is formed around a central region, and wherein the central region comprises a material different from the semiconductor substrate.

3. The device of claim 2, wherein the central region comprises a magnetic material.

4. The device of claim 1, wherein the through substrate conductor coil is formed around a central region, and wherein the central region comprises a cavity.

5. The device of claim 1, wherein the through substrate conductor coil comprises a conductive material disposed within a through substrate opening, the conductive material being isolated from the substrate by an insulating liner.

6. The device of claim 5, wherein the conductive material comprises a non-magnetic metallic material.

7. The device of claim 1, wherein the through substrate conductor coil comprises a spiral coil.

8. The device of claim 1, wherein the through substrate conductor coil comprises a concentric coil.

9. The device of claim 1, wherein the through substrate conductor coil forms an inductor.

10. The device of claim 1, further comprising through substrate conductor coil disposed in the first region, the through substrate conductor coil inductively coupled to the through substrate conductor coil.

11. The device of claim 1, wherein the through substrate via extends from a top surface of the semiconductor substrate to beyond an opposite bottom surface of the semiconductor substrate to a first metal line disposed over the semiconductor substrate, wherein the through substrate coil extends through the semiconductor substrate from the top surface of the semiconductor substrate to beyond the bottom surface of the semiconductor substrate to a second metal line disposed over the semiconductor substrate.

12. The device of claim 1, wherein the insulating liner and the sidewall insulating liner comprise substantially the same thickness.

13. A semiconductor device comprising:

a first through substrate opening within a semiconductor substrate, the first through substrate opening extending from a bottom surface of the semiconductor substrate to an opposite top surface of the semiconductor substrate, wherein, in a plane parallel to the bottom surface, the first through substrate opening includes a ring shaped through substrate trench opening extending around a central region, wherein the ring shaped through substrate trench opening extends from the bottom surface of the semiconductor substrate to the top surface of the semiconductor substrate;

an insulating material lining sidewalls of the first through substrate opening; and

a conductive material at least partially filling the first through substrate opening, wherein the first through substrate opening comprises only a single coil.

14. The device of claim 13, wherein the conductive material forms the coil for an inductor, and wherein the inductor comprises the central region surrounded by the coil and the first through substrate opening filled with the conductive material.

15. The device of claim 13, further comprising a second through substrate opening in the central region, wherein the first through substrate opening is formed around the central region.

16. The device of claim 15, further comprising a magnetic material at least partially filling the second through substrate opening.

17. The device of claim 13, wherein the first through substrate opening comprises an opening for a spiral coil, and wherein the ring shaped through substrate trench opening comprises a spiral design.

18. The device of claim 13, wherein the first through substrate opening comprises another ring shaped through substrate trench opening extending around the central region and the ring shaped through substrate trench opening, and wherein the ring shaped through substrate trench opening and the another ring shaped through substrate trench opening form a part of an opening for a concentric coil.

19. A semiconductor device comprising:

a first, a second, and a third through substrate openings disposed within a semiconductor substrate, the first through substrate opening being disposed at least partially around the second through substrate opening, the first, the second, and the third through substrate openings extending from a bottom surface of a semiconductor substrate to an opposite top surface of the semiconductor substrate;

a first liner disposed within the first through substrate opening;

a second liner disposed within the second through substrate opening;

a third liner disposed within the third through substrate opening;

an insulating material lining the first, the second, and the third through substrate openings;

a conductive material at least partially filling the first and the third through substrate openings to form a portion of an inductor and a portion of a through substrate via; and

spacers disposed on the first, the second, and the third through substrate openings.

20. The device of claim 19, further comprising a magnetic material filling the second through substrate opening.

21. The device of claim 19, wherein the conductive material comprises a non-magnetic metallic material.

22. The device of claim 19, wherein the first through substrate opening and the third through substrate have substantially the same width along the bottom surface, and wherein the first through substrate opening is narrower than the second through substrate.

23. A semiconductor device comprising:

a first, a second, and a third through substrate openings disposed within a semiconductor substrate, the first through substrate opening being disposed at least partially around the second through substrate opening, the first, the second, and the third through substrate openings extending from a bottom surface of a semiconductor substrate to an opposite top surface of the semiconductor substrate;

a first liner disposed within the first through substrate opening;

a second liner disposed within the second through substrate opening;

a third liner disposed within the third through substrate opening;

an insulating material lining the first, the second, and the third through substrate openings;

a conductive material at least partially filling the first and the third through substrate openings to form a portion of an inductor and a portion of a through substrate via;

a fourth through substrate opening disposed in the semiconductor substrate, the fourth through substrate opening being disposed around a first semiconductor die region comprising the first, the second, and the third through substrate openings, the fourth through substrate opening extending from the bottom surface of the semiconductor substrate to the top surface of the semiconductor substrate; and

an insulating material lining the fourth through substrate opening, wherein the fourth through substrate opening extends through a metallization layer disposed over the top surface of the semiconductor substrate to separate the first semiconductor die region from a remaining portion of the semiconductor substrate.

24. The device of claim 23, further comprising spacers disposed on the first, the second, and the third through substrate openings.

25. A semiconductor device comprising:

a first through substrate opening within a semiconductor substrate, the first through substrate opening extending from a bottom surface of the semiconductor substrate to an opposite top surface of the semiconductor substrate;

an insulating material lining sidewalls of the first through substrate opening;

a coil for an inductor disposed in the semiconductor substrate, the coil comprising a conductive material at least partially filling the first through substrate opening, wherein the inductor comprises a central region surrounded by the coil; and

a second coil disposed in a metallization layer above the top surface of the semiconductor substrate, the second coil being inductive coupled to the coil, wherein a major sidewall of the semiconductor substrate is lined with the insulating material.

26. The device of claim 25, wherein the central region comprises a second through substrate opening filled at least partially with a magnetic material different from the conductive material, wherein the conductive material comprises a non-magnetic metallic material.

27. The device of claim 26, wherein the first through substrate opening is narrower than the second through substrate.