Method for producing group III nitride semiconductor and template substrate

• US 9,196,687 B2
• Filed: 02/19/2014
• Issued: 11/24/2015
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Nakada, Naoyuki, Okuno, Koji, Ushida, Yasuhisa
• Primary Examiner(s): WOLDEGEORGIS, ERMIAS T
• Application Number:
  US14/183,809
• Publication Number:
  US 20140167222A1
• Time in Patent Office: 643 Days
• Field of Search: 257/201, 257/507, 257/615, 257/E21.09, 257/E21.091, 257/E21.097, 257/E29.005, 257/E29.089, 438/478, 438/479, 438/481, 438/503, 438/689
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds

Abstract

A semiconductor substrate includes a sapphire substrate including an a-plane main surface and a groove in a surface thereof, the groove includes side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. Both side surfaces of the groove assume a c-plane of sapphire. An axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor. A plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.

Claims

1. A semiconductor substrate, comprising:

a sapphire substrate including an a-plane main surface and comprising a groove in a surface thereof, the groove including side surfaces and a bottom surface; and

a Group III nitride semiconductor layer formed on the sapphire substrate,

wherein both side surfaces of the groove assume a c-plane of sapphire,

wherein an axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor, and

wherein a plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.

2. A semiconductor substrate according to claim 1, wherein the surface of the sapphire substrate is nitrided, and the Group III nitride semiconductor layer is formed without depositing a buffer layer.

3. A semiconductor substrate according to claim 1, wherein the sapphire substrate comprises a buffer film formed along an entire surface thereof, and the Group III nitride semiconductor layer is formed via a buffer film on the sapphire substrate.

4. A semiconductor substrate according to claim 1, wherein the groove is formed in a stripe pattern.

5. A semiconductor substrate according to claim 3, wherein the buffer film comprises Al_xGa_1-xN (0≦

x≦

1).

6. A semiconductor substrate according to claim 5, wherein the buffer film has a thickness of 150 Å

or less.

7. A semiconductor substrate according to claim 1, wherein a crystallographic orientation relationship of the semiconductor substrate is represented as (the main surface of the sapphire substrate, said one of the side surfaces of the groove, a crystal axis of GaN in a direction perpendicular to said one of the side surfaces of the groove, and a main surface of GaN parallel to the main surface of the sapphire substrate).

8. A semiconductor substrate according to claim 7, wherein the crystallographic orientation relationship of the semiconductor substrate is represented as (a, c, c, m).