High uniformity screen and epitaxial layers for CMOS devices

• US 9,196,727 B2
• Filed: 11/06/2014
• Issued: 11/24/2015
• Est. Priority Date: 12/22/2011
• Status: Expired due to Fees

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Thompson, Scott E., Shifren, Lucian, Ranade, Pushkar, Liu, Yujie, Kim, Sung Hwan, Wang, Lingquan, Zhao, Dalong, Bakhishev, Teymur, Hoffmann, Thomas, Pradhan, Sameer, Duane, Michael
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US14/534,595
• Publication Number:
  US 20150061012A1
• Time in Patent Office: 383 Days
• Field of Search: 257/344, 257/369, 257/E21.437, 257/E29.266
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

Claims

1. A semiconductor transistor comprising:

a gate having a gate dielectric extending over a defined area, the gate having an effective gate length;

an epitaxial layer positioned on a semiconductor substrate below the defined area of the gate, the epitaxial layer containing a substantially undoped channel positioned below the gate dielectric and extending between a source and a drain, the substantially undoped channel having a preselected thickness; and

a screen layer formed at least in part in the semiconductor substrate with a depth of the screen layer set a preselected distance below the defined area of the gate such that the distance is a fraction of the effective gate length of the transistor and varying no more than one nanometer in uniformity across the substantially undoped channel, the screen layer having a defined thickness preselected such that the bottom of the screen layer is above the bottom of the source and drain and wherein the screen layer extends laterally to and contacts both the source and the drain.

2. The semiconductor transistor of claim 1, wherein the epitaxial layer has a thickness varying no more than one half nanometer over the defined gate area.

3. The semiconductor transistor of claim 1, wherein the depth of the screen layer below the defined area of the gate of the transistor varies no more than one half nanometer over the defined gate area.

4. The semiconductor transistor of claim 1, wherein the screen layer has a dopant concentration between 1×

1018 and 5×

1019 atoms per cubic centimeter, and further has a defined thickness of between five and twenty nanometers that varies no more than three nanometers.

5. The semiconductor transistor of claim 1, further comprising:

a shallow lightly doped drain region in the channel on either side of the gate and extending a defined distance inward from the outer edges of the gate;

a deep lightly doped drain region on either side of the gate at a depth of the screening layer.

6. A semiconductor die comprising

a plurality of transistors formed to include a common epitaxial layer positioned on a semiconductor substrate, with each of the plurality of transistors containing a substantially undoped channel positioned below a gate dielectric and between a source and a drain;

and

a screen layer formed at least in part in the semiconductor substrate, with depth of the screen layer below the gate dielectric of the plurality of transistors varying no more than two (2) nanometers.

7. The semiconductor die of claim 6, further comprising:

a shallow lightly doped drain region in the channel on either side of the gate dielectric and extending a defined distance inward from the outer edges of the gate dielectric;

a deep lightly doped drain region on either side of the gate dielectric at a depth of the screening layer.