Semiconductor device

• US 9,196,744 B2
• Filed: 07/31/2014
• Issued: 11/24/2015
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya, Kurata, Motomu, Kuwabara, Hideaki, Terashima, Mari
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/448,024
• Publication Number:
  US 20140339552A1
• Time in Patent Office: 481 Days
• Field of Search: 257/43, 438/151, 438/161
• US Class Current: 1/1
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.

Claims

1. A semiconductor device comprising:

a source electrode layer and a drain electrode layer;

an oxide semiconductor layer comprising a first impurity region, a second impurity region, and a channel region sandwiched between the first impurity region and the second impurity region, wherein a side surface of the first impurity region is in contact with the source electrode layer in a channel-length direction and a side surface of the second impurity region is in contact with the drain electrode layer in the channel-length direction;

a gate insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region;

a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer, wherein at least part of the second portion overlaps with the source electrode layer and the drain electrode layer;

a sidewall insulating layer in contact with an outer side surface of the first portion and an upper surface of the second portion, wherein the sidewall insulating layer is not in contact with the gate electrode layer; and

wherein the source electrode layer has a tapered shape,

wherein the drain electrode layer has a tapered shape,

wherein a first edge of the oxide semiconductor layer overlap with the source electrode layer, and

wherein a second edge of the oxide semiconductor layer overlap with the drain electrode layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

3. A semiconductor device comprising:

a source electrode layer and a drain electrode layer;

an oxide semiconductor layer;

a gate insulating layer over and in contact with the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the source electrode layer has a tapered shape,

wherein the drain electrode layer has a tapered shape,

wherein a first edge of the oxide semiconductor layer overlaps with the source electrode layer, and

wherein a second edge of the oxide semiconductor layer overlaps with the drain electrode layer,

further comprising a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer.

4. The semiconductor device according to claim 3, wherein the oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

5. The semiconductor device according to claim 3, wherein the oxide semiconductor layer includes a first impurity region, a second impurity region, and a channel region sandwiched between the first impurity region and the second impurity region.

6. The semiconductor device according to claim 3, wherein the gate insulating layer is over and in contact with the source electrode layer.

7. The semiconductor device according to claim 3, wherein the gate insulating layer is over and in contact with the drain electrode layer.

8. The semiconductor device according to claim 3, further comprising a sidewall insulating layer in contact, with an outer side surface of the first portion and an upper surface of the second portion, wherein the sidewall insulating layer is not in contact with the gate electrode layer.