Pseudo-envelope following power management system

• US 9,197,165 B2
• Filed: 07/23/2013
• Issued: 11/24/2015
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Kay, Michael R.
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US13/948,291
• Publication Number:
  US 20130307617A1
• Time in Patent Office: 854 Days
• Field of Search: 330/127, 330/297, 455/127.1
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03F 1/0238 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03G 3/004 Control by varying the supply voltage

Abstract

Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier.

Claims

1. A power management system for an RF power amplifier comprising:

a parallel amplifier including an amplifier in communication with a power amplifier supply voltage; and

a multi-level charge pump buck converter comprising;

a switcher control circuit configured to output a logic level indication;

a frequency lock loop (FLL) in communication with the switcher control circuit and receiving the logic level indication; and

a switching voltage output in communication with the power amplifier supply voltage, wherein the multi-level charge pump buck converter is configured to shunt the switching voltage output to ground in a first operational state, provide a direct current input voltage to the switching voltage output in a second operational state, provide 1.5 times the direct current input voltage to the switching voltage output in a third operational state, and provide 2 times the direct current input voltage to the switching voltage output in a fourth operational state.

2. The power management system of claim 1 wherein the multi-level charge pump buck converter further comprises a multi-level charge pump circuit configured to receive a DC voltage.

3. The power management system of claim 1 wherein the FLL is configured to receive a clock signal.

4. The power management system of claim 1 wherein the multi-level charge pump buck converter further comprises a switching circuit.

5. The power management system of claim 4, wherein the switching circuit comprises a series switch and a shunt switch.

6. The power management system of claim 1 wherein the switcher control circuit comprises a threshold detector and control circuit configured to operate the multi-level charge pump buck converter in different modes of operation.

7. The power management system of claim 6 wherein the switcher control circuit further comprises a programmable threshold circuit configured to provide thresholds to the threshold detector and control circuit.

8. The power management system of claim 6 wherein the threshold detector and control circuit are configured to receive an amplifier circuit output current estimate (I_PAWA—

<sub>OUT—

EST</sub>).

9. The power management system of claim 8 wherein the threshold detector and control circuit are configured to also receive a threshold offset current (I_THRESHOLD—

_OFFSET).

10. The power management system of claim 6 further comprising a summing circuit configured to subtract a threshold offset current from I_PAWA—

<sub>OUT—

EST</sub> to generate a compensated parallel amplifier circuit output current estimate (I<sub>PAWA—

COMP</sub>).

11. The power management system of claim 10 wherein the multi-level charge pump buck converter shifts from a series output mode to a first boost output mode if I_PAWA—

_COMP is greater than a first boost level threshold.

12. The power management system of claim 11 wherein the multi-level charge pump buck converter shifts from the first boost output mode to the series output mode if I_PAWA—

_COMP is less than the first boost level threshold.

13. The power management system of claim 11 wherein the multi-level charge pump buck converter shifts from the first boost output mode to a second boost output mode if I_PAWA—

_COMP is greater than a second boost level threshold.

14. The power management system of claim 13 wherein the multi-level charge pump buck converter shifts from the second boost output mode to the series output mode if I_PAWA—

_COMP is less than the first boost level threshold.

15. The power management system of claim 10 wherein the multi-level charge pump buck converter shifts from a series output mode to a shunt output mode if I_PAWA—

_COMP is less than a series level threshold.

16. The power management system of claim 15 wherein the multi-level charge pump buck converter shifts from the shunt output mode to the series output mode if I_PAWA—

_COMP is greater than the shunt level threshold.