Methods and apparatuses for use in tuning reactance in a circuit device

• US 9,197,194 B2
• Filed: 08/27/2012
• Issued: 11/24/2015
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Reedy, Ronald Eugene, Nobbe, Dan William, Ranta, Tero Tapio, Liss, Cheryl V., Kovac, David
• Primary Examiner(s): Takaoka, Dean
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US13/595,893
• Publication Number:
  US 20130222075A1
• Time in Patent Office: 1,184 Days
• Field of Search: 333/32, 333/172
• US Class Current: 1/1
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Claims

1. A tunable inductor, comprising:

a first RF terminal;

a second RF terminal;

a plurality of inductive elements connected therebetween, wherein each inductive element is an inductor or a portion thereof;

a plurality of switches connected with the plurality of inductive elements, wherein each switch in the plurality of switches is configured, during operation, to receive a control signal, the control signal controlling inductance applied between the first RF terminal and the second RF terminal by turning on or off switches in the plurality of switches; and

at least one bypass switch comprising a plurality of series connected switches, wherein the at least one bypass switch is connected to a bypass node within the tunable inductor via a first terminal of the bypass switch and to the second RF terminal via a second terminal of the bypass switch, the bypass switch being configured to selectively exclude, via a first mode of operation of the bypass switch, and to include, via a second mode of operation of the bypass switch, at least two inductive elements of the plurality of inductive elements and corresponding connected switches in a conduction path between the first RF terminal and the second RF terminal,

wherein;

at least one inductive element in the plurality of inductive elements is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween,

each switch of the plurality of switches has a resistance and each inductive element of the plurality of inductive elements has an inductance, each resistance and each inductance being selected based on a desired quality factor for the tunable inductor, and

for a same inductance applied between the first RF terminal and the second RF terminal, the at least one bypass switch provides a first quality factor for the tunable inductor in the first mode of operation and a second quality factor for the tunable inductor in the second mode of operation, the first quality factor being higher than the second quality factor.

2. The tunable inductor according to claim 1, wherein:

each inductive element in the plurality of inductive elements is connected with at least one switch in the plurality of switches, and

each switch in the at least one switch is configured, during operation, to receive the same control signal.

3. The tunable inductor according to claim 2, wherein each switch in the at least one switch is serially connected therebetween.

4. The tunable inductor according to claim 1, wherein at least one inductive element in the plurality of inductive elements is connected in parallel with at least one switch in the plurality of switches.

5. The tunable inductor according to claim 1, wherein the plurality of inductive elements are serially connected therebetween.

6. The tunable inductor according to claim 1, wherein at least one inductive element in the plurality of inductive elements is serially connected with at least one switch in the plurality of switches.

7. The tunable inductor according to claim 1, wherein at least one inductive element in the plurality of inductive elements is connected in parallel with another inductive element in the plurality of inductive elements.

8. The tunable inductor according to claim 1, wherein each inductive element in the plurality of inductive elements is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.

9. The tunable inductor according to claim 1, wherein

the plurality of inductive elements are connected in parallel or in series with each other.

10. The tunable inductor according to claim 1, the plurality of inductive elements comprising at least a first inductive element, a second inductive element, and a third inductive element, wherein inductance values of the first inductive element and the second inductive element differ by a first scaling factor and inductance values of the second inductive element and the third inductive element differ by a second scaling factor.

11. The tunable inductor according to claim 10, wherein the first scaling factor is equal to the second scaling factor.

12. The tunable inductor according to claim 1, wherein at least one switch in the plurality of switches is selected from the group consisting of a field effect transistor, an accumulated charge control field effect transistor, a microelectromechanical system (MEMS) switch, a diode, and a bipolar junction transistor.

13. The tunable inductor according to claim 1, wherein each inductive element in the plurality of inductive elements is either a lumped element or a distributed element.

14. The tunable inductor according to claim 1, wherein the plurality of switches is integrated onto a chip and each inductive element in the plurality of inductive elements is either integrated onto the chip or off-chip.

15. The tunable inductor according to claim 14, wherein the plurality of switches and each inductive element in the plurality of inductive elements are integrated onto the chip.

16. The tunable inductor according to claim 14, wherein the chip is a silicon-on-insulator chip.

17. The tunable inductor according to claim 14, wherein the chip is a silicon-on-sapphire chip.

18. A system for tuning reactance to generate a target signal, the system comprising:

the circuital arrangement according to claim 1, wherein the circuital arrangement is configured, during operation, to receive a first signal and generate a second signal; and

a controller configured, during operation, to provide a plurality of control signals to the circuital arrangement, wherein the plurality of control signals is a function of the second signal and the target signal.

19. A method for tuning reactance of a circuital arrangement to generate a target signal, the method comprising:

providing the circuital arrangement according to claim 1;

applying a first signal and a plurality of control signals to the circuital arrangement, wherein reactance of the circuital arrangement is a function of the plurality of control signals;

generating a second signal based on the applying; and

adjusting the plurality of control signals based on the second signal and the target signal.

20. The tunable inductor of claim 1, wherein the plurality of switches are field effect transistor (FET) switches and the resistance is selected by controlling a width of each FET switch.

21. A circuital arrangement with a tunable impedance, the circuital arrangement comprising:

a first RF terminal;

a second RF terminal;

a fixed reactance, wherein the fixed reactance comprises a fixed inductor or a portion thereof and/or a fixed capacitor;

a plurality of switches connected in parallel or series with the fixed reactance, wherein each switch in the plurality of switches is configured, during operation, to receive a control signal;

a plurality of individual reactances connected with the plurality of switches, wherein at least one individual reactance is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween; and

at least one bypass switch comprising a plurality of series connected switches, wherein the at least one bypass switch is connected to a first individual reactance of the plurality of individual reactances via a first terminal of the bypass switch and to a second individual reactance of the plurality of reactances via a second terminal of the bypass switch, the bypass switch being configured to selectively exclude and include, via a bypass control signal, a conduction path comprising the first and the second individual reactances in the circuital arrangement,

wherein;

whether impedance of a particular individual reactance among the plurality of individual reactances contributes to impedance of the circuital arrangement is based on a control signal received, during operation, by a particular switch in the plurality of switches that is connected with the particular individual reactance, the control signal associated with the particular switch turns on or off the particular switch,

each switch of the plurality of switches has a resistance and each individual reactance of the plurality of individual reactances has a reactance value, each resistance and each reactance value being selected based on a desired quality factor for the tunable impedance, and

for a same impedance provided by the plurality of individual reactances via the control signal to the plurality of switches, a first associated quality factor to the same impedance is provided when the bypass switch excludes the conduction path comprising the first and the second individual reactances, and a second associated quality factor to the same impedance is provided when the bypass switch includes the conduction path comprising the first and the second individual reactances, the first associated quality factor being higher than the second associated quality factor.

22. The circuital arrangement according to claim 21, wherein:

each individual reactance in the plurality of individual reactances is connected with at least one switch in the plurality of switches, and

each switch in the at least one switch is configured, during operation, to receive the same control signal.

23. The circuital arrangement according to claim 22, wherein each switch in the at least one switch is serially connected therebetween.

24. The circuital arrangement according to claim 21, wherein, when a switch connected with a particular individual reactance is turned on, impedance of the particular individual reactance contributes to impedance of the circuital arrangement.

25. The circuital arrangement according to claim 21, wherein, when a switch connected with a particular individual reactance is turned off, impedance of the particular individual reactance contributes to impedance of the circuital arrangement.

26. The circuital arrangement according to claim 21, further comprising a plurality of resistors connected with the plurality of switches.

27. The circuital arrangement according to claim 21, wherein each individual reactance in the plurality of individual reactances is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.

28. The circuital arrangement according to claim 21, wherein at least one switch in the plurality of switches is selected from the group consisting of a field effect transistor, an accumulated charge control field effect transistor, a microelectromechanical system (MEMS) switch, a diode, and a bipolar junction transistor.

29. The circuital arrangement according to claim 21, wherein the fixed reactance and each individual reactance in the plurality of individual reactances is either a lumped element or a distributed element.

30. The circuital arrangement according to claim 21, wherein:

the plurality of switches is integrated onto a chip, and

the fixed reactance and each individual reactance in the plurality of individual reactances is either integrated onto the chip or off-chip.

31. The circuital arrangement according to claim 30, wherein the plurality of switches, the fixed reactance, and each inductive reactance in the plurality of individual reactances are integrated onto the chip.

32. The circuital arrangement according to claim 30, wherein the chip is a silicon-on-insulator chip.

33. The circuital arrangement according to claim 30, wherein the chip is a silicon-on-sapphire chip.

34. A system for tuning impedance to generate a target signal, the system comprising:

the circuital arrangement according to claim 21, wherein the circuital arrangement is configured, during operation, to receive a first signal and generate a second signal; and

a controller configured, during operation, to provide a plurality of control signals to the circuital arrangement, wherein the plurality of control signals is a function of the second signal and the target signal.

35. A method for tuning impedance of a circuital arrangement to generate a target signal, the method comprising:

providing the circuital arrangement according to claim 21;

applying a first signal and a plurality of control signals to the circuital arrangement, wherein impedance of the circuital arrangement is a function of the plurality of control signals;

generating a second signal based on the applying; and

adjusting the plurality of control signals based on the second signal and the target signal.

36. The circuital arrangement of claim 21, wherein the plurality of switches are field effect transistor (FET) switches and the resistance is selected by controlling a width of each FET switch.

37. A method for tuning inductance of a device, comprising:

providing a plurality of inductive elements connected therebetween, wherein each inductive element is an inductor or a portion thereof;

providing a plurality of switches connected with the plurality of inductive elements;

providing a bypass switch comprising a plurality of series connected switches, wherein the bypass switch is connected to a first inductive element of the plurality of inductive elements via a first terminal of the bypass switch and to a second inductive element of the plurality of inductive elements via a second terminal of the bypass switch, the bypass switch being configured to selectively exclude and include, via a bypass control signal, a conduction path comprising the first and the second inductive elements;

selecting a resistance for each switch of the plurality of switches based on a desired quality factor for the inductance of the device;

selecting an inductance for each inductive element of the plurality of inductive elements based on the desired quality factor for the inductance of the device;

applying a plurality of control signals to the plurality of switches, wherein each control signal turns on or off one or more switches in the plurality of switches, thus tuning the inductance of the device;

based on the applying the plurality of control signals to the plurality of switches, applying the bypass control signal to the bypass switch; and

based on the applying of the bypass control signal, reducing the quality factor for the inductance of the device,

wherein;

whether a particular inductive element in the plurality of inductive elements contributes to inductance of the device is based on a control signal received by a particular switch in the plurality of switches that is connected with the particular inductive element, and

at least one inductive element in the plurality of inductive elements is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.

38. The method according to claim 37, wherein an inductive element in the plurality of inductive elements is connected with at least one switch in the plurality of switches, and wherein the applying comprises:

applying the same control signal to each switch in the at least one switch.

39. The method according to claim 38, wherein each switch in the at least one switch is serially connected therebetween.

40. The method according to claim 37, wherein an inductive element contributes to inductance of the device when a switch connected with the inductive element is turned on.

41. The method according to claim 37, wherein an inductive element contributes to inductance of the device when a switch connected with the inductive element is turned off.

42. The method of claim 37, wherein the plurality of switches are field effect transistor (FET) switches and the selecting a resistance is carried out by controlling a width of each FET switch.

43. A method for tuning impedance of a device, comprising:

providing a fixed reactance, wherein the fixed reactance comprises a fixed inductor or a portion thereof and/or a fixed capacitor;

providing a plurality of switches connected in parallel or series with the fixed reactance;

providing a plurality of individual reactances connected with the plurality of switches;

providing a bypass switch comprising a plurality of series connected switches, wherein the bypass switch is connected to a first individual reactance of the plurality of individual reactances via a first terminal of the bypass switch and to a second individual reactance of the plurality of individual reactances via a second terminal of the bypass switch, the bypass switch being configured to selectively exclude and include, via a bypass control signal, a conduction path comprising the first and the second individual reactances;

selecting a resistance for each switch of the plurality of switches based on a desired quality factor for the inductance of the device;

selecting a reactance value for each individual reactance of the plurality of individual reactances based on the desired quality factor for the inductance of the device; and

applying a plurality of control signals to the plurality of switches, wherein each control signal turns on or off one or more switches in the plurality of switches, thus tuning the impedance of the device,

based on the applying the plurality of control signals to the plurality of switches, applying the bypass control signal to the bypass switch; and

based on the applying of the bypass control signal, reducing the quality factor for the inductance of the device,

wherein;

whether impedance of a particular individual reactance among the plurality of individual reactances contributes to impedance of the device is based on a control signal received by a particular switch in the plurality of switches that is connected with the particular individual reactance, and

at least one individual reactance is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.

44. The method according to claim 43, wherein an individual reactance in the plurality of individual reactances is connected with at least one switch in the plurality of switches, and wherein the applying comprises:

applying the same control signal to each switch in the at least one switch.

45. The method according to claim 43, wherein each switch in the at least one switch is serially connected therebetween.

46. The method of claim 43, wherein the plurality of switches are field effect transistor (FET) switches and the selecting a resistance is carried out by controlling a width of each FET switch.

47. A system for tuning impedance to generate a target signal, the system comprising:

a tunable element configured, during operation, to receive a first signal and generate a second signal; and

a controller configured, during operation, to provide a plurality of control signals to the tunable element, wherein;

impedance of the tunable element is a function of the plurality of control signals and the plurality of control signals is a function of the second signal and the target signal,

for a same value of the impedance of the tunable element, a first value or a second value, lower than the first value, of a quality factor of the tunable element is a function of an ON or OFF state of a bypass switch comprising a plurality of series connected switches coupled to the tunable element,

the tunable element comprises a plurality of tunable reactances, each tunable reactance of the plurality of tunable reactances being a tunable capacitor or a tunable inductor,

the each tunable reactance has a value selected based on a desired quality factor for the tunable element,

the tunable element comprises a plurality of switches, each switch of the plurality of switches having a resistance selected based on the desired quality factor for the tunable element.

48. The system according to claim 47, wherein:

each tunable reactance is either a lumped element or a distributed element.

49. The system according to claim 47, wherein:

each tunable reactance is either integrated on a chip or off-chip.

50. The system according to claim 49, wherein the chip is a silicon-on-insulator chip.

51. The system according to claim 49, wherein the chip is a silicon-on-sapphire chip.

52. The system of claim 47, wherein the plurality of switches are field effect transistor (FET) switches and the resistance is selected by controlling a width of each FET switch.

53. A method for tuning impedance to generate a target signal, the method comprising:

providing a tunable element, the tunable element comprising;

(i) a plurality of switches;

(ii) at least one tunable reactance, the at least one tunable reactance being at least one tunable capacitor or at least one tunable inductor comprising a plurality of individual reactances; and

(iii) at least one bypass switch coupled to the at least one tunable reactance, the bypass switch comprising a plurality of series connected switches, wherein the bypass switch is connected to a first individual reactance of the plurality of individual reactances via a first terminal of the bypass switch and to a second individual reactance of the plurality of individual reactances via a second terminal of the bypass switch, the bypass switch being configured to selectively exclude and include, via a bypass control signal, a conduction path comprising the first and the second individual reactances in the at least one tunable reactance;

selecting a desired quality factor for the tunable element;

selecting a resistance for each switch of the plurality of switches, based on the desired quality factor;

selecting a reactance value for the at least one tunable reactance, based on the desired quality factor;

applying a first signal and a plurality of control signals to the tunable element, wherein impedance of the tunable element is a function of the plurality of control signals applied to the plurality;

generating a second signal based on the applying;

adjusting the plurality of control signals based on the second signal and the target signal, and

applying the bypass control signal to the bypass switch to reduce a quality factor of the tunable element.

54. The method of claim 53, wherein the plurality of switches are field effect transistor (FET) switches and the selecting a resistance is carried out by controlling a width of each FET switch.