Re-circulating time-to-digital converter (TDC)

• US 9,197,402 B2
• Filed: 04/10/2012
• Issued: 11/24/2015
• Est. Priority Date: 04/10/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Hyung Seok, Ravi, Ashoke, Li, William Y., Chandrashekar, Kailash
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US13/997,229
• Publication Number:
  US 20140333358A1
• Time in Patent Office: 1,323 Days
• Field of Search: 341/155, 341/144, 341/118, 341/120, 341/110, 341/111
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.

Claims

1. A re-circulating time-to-digital converter (TDC), comprising:

a triggered reference ring oscillator (TRRO) configured, when triggered by a reference signal edge, to generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period; and

a delay module configured to store, in a plurality of latches, samples of a VCO signal clocked by the periodic ring oscillator signal, wherein each latch is configured to generate an output of the sample, and each latch output represents a time difference polarity between the VCO signal and the periodic ring oscillator signal.

2. The re-circulating TDC of claim 1, wherein the delay module is configured as at least one of a shift register and the plurality of latches to form a cascade of flip flops, and each of the samples of the VCO clock includes digital state information.

3. The re-circulating TDC of claim 1, wherein the number of latches is at least 1.5 times the TDC sample number, and the TDC sample number is a positive integer of samples per VCO period.

4. The re-circulating TDC of claim 1, wherein the ring oscillator period is shorter than the VCO period, and the ring oscillator period T_ref.fing is represented by (N_s−

1)/N_s*T_vco is the VCO period, N_s is a TDC sample number, and the TDC sample number is a positive integer of samples per the VCO period.

5. The re-circulating TDC of claim 1, wherein the ring oscillator period is longer than the VCO period, and the ring oscillator period T_ref.ring is represented by (N_s+1)/N_s*T_vco, where T_vco is the VCO period, N_s is a TDC sample number, and the TDC sample number is a positive integer of samples per the VCO period.

6. The re-circulating TDC of claim 1, wherein the ring oscillator period is substantially within one TDC sample width of a voltage-controlled oscillator (VCO) period, wherein the TDC sample width is one over a TDC sample number N_s times the VCO period, and the TDC sample number is a positive integer of samples per VCO period.

7. The re-circulating TDC of claim 6, wherein the re-circulating TDC has a resolution of B-bits, and the TDC sample number N_s is represented by 2^B.

8. The re-circulating TDC of claim 1, further comprising an output module configured to output the samples of the plurality of latches of the delay module, wherein the outputs are latched after a sampling time interval, where the sampling time interval is a VCO period normalized time interval plus a state transition time interval, where the VCO period normalized time interval is substantially the TDC sample number times the VCO period, the TDC sample number is a positive integer of samples per VCO period, and the state transition time interval is a variable time interval after the VCO period normalized time interval when a specified latch transitions to a different digital state.

9. The re-circulating TDC of claim 8, further comprising:

a digital frequency lock module configured to generate a ring oscillator control signal, wherein the ring oscillator control signal sets the ring oscillator period for the triggered reference ring oscillator; and

a TDC post-process module configured to generate a TDC output, wherein the TDC output is a binary representation of a phase difference between a reference signal and a VCO signal.

10. The re-circulating TDC of claim 1, wherein the triggered reference ring oscillator is configured to cease clocking the periodic ring oscillator signal and reset an oscillator output with a reset signal.

11. The re-circulating TDC of claim 1, further comprising a reset module configured to reset the triggered reference ring oscillator and a delay module, wherein each latch of the delay module is set to a predetermined state when the delay module is reset, and the reset module further comprises:

a digitally controlled delay line (DCDL) configured to generate a reset signal when a specified latch from the delay module transitions to a different digital state; and

a digital gate configured to generate a reset signal from the DCDL or an external reset command received external to the re-circulating TDC, wherein the reset signal instructs the triggered reference ring oscillator to cease clocking the periodic ring oscillator signal.

12. The re-circulating TDC of claim 11, wherein the specified latch is a most significant bit (MSB) of the plurality of latches of the delay module.

13. The re-circulating TDC of claim 1, further comprising a tuning module configured to interpolate a desired VCO frequency and reduce a time for the triggered reference ring oscillator to converge on the desired VCO frequency.

14. The re-circulating TDC of claim 13, wherein the tuning module further comprises:

a memory configured to store discrete initialization tuning settings for the triggered reference ring oscillator; and

a quadri-correlator configured to determine a polarity of a frequency difference between the VCO signal and the periodic ring oscillator signal and maintain one signal frequency, either a VCO signal frequency or a periodic ring oscillator signal frequency, higher than the other signal frequency.

15. The re-circulating TDC of claim 1, wherein the re-circulating TDC is configured in a phase locked loop (PLL) to generate a clock frequency within a band of an Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, IEEE 802.16 standard, and third generation partnership project (3GPP) long term evolution (LTE) standard.

16. The re-circulating TDC of claim 1, wherein the re-circulating TDC is included in a mobile device configured to connect to at least one of a wireless local area network (WLAN), a wireless personal area network (WPAN), and a wireless wide area network (WWAN), wherein the mobile device includes an antenna, a touch sensitive display screen, a speaker, a microphone, a graphics processor, an application processor, internal memory, a non-volatile memory port, or combinations thereof.

17. An all-digital phase locked loop (ADPLL), comprising:

a digital phase/frequency detector configured to integrate frequency error by comparing a frequency word input to a differentiated TDC output in a feedback loop which is proportional to a frequency difference between the frequency word and the differentiated TDC output;

a digital loop filter configured to generate a filtered phase error signal by low-pass filtering the phase error signal;

a digital-to-analog converter (DAC) configured to convert the filtered phase error signal into a voltage input for a VCO;

the VCO configured to generate a periodic VCO signal at a specified frequency, wherein the voltage input is used to converge the VCO frequency to the specified frequency;

the re-circulating TDC of claim 1, configured to generate a TDC output signal from the VCO signal and the reference signal; and

a differenciator configured to generate the differentiated TDC output by differentiating the TDC output signal.

18. A re-circulating time-to-digital converter (TDC), comprising:

a triggered reference ring oscillator (TRRO) configured, when triggered by a reference signal edge, to generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period;

a digital frequency lock module configured to generate a ring oscillator control signal, wherein the ring oscillator control signal sets the ring oscillator period for the triggered reference ring oscillator; and

a TDC post-process module configured to generate a TDC output, wherein the TDC output is a binary representation of a phase difference between a reference signal and a VCO signal.

19. The re-circulating TDC of claim 18, wherein the ring oscillator period is substantially within one TDC sample width of a voltage-controlled oscillator (VCO) period, wherein the TDC sample width is one over a TDC sample number N_s times the VCO period, and the TDC sample number is a positive integer of samples per VCO period.

20. The re-circulating TDC of claim 18, wherein the digital frequency lock module is further configured to generate an instantaneous VCO period T_pn normalized to a TDC resolution and a VCO period normalized error T_pn.err from the outputs of the output module, wherein the VCO period normalized error is a TDC sample number N_s subtracted from the instantaneous VCO period, and the TDC sample number N_s is a positive integer of samples per VCO period.

21. The re-circulating TDC of claim 18, wherein the digital frequency lock module further comprises:

an adder configured to subtract a TDC sample number N_s from an instantaneous VCO period T_pn normalized to a TDC resolution to generate a VCO period normalized error T_pn.err, wherein the TDC sample number N_s is a positive integer of samples per VCO period;

an accumulator configured to generate an integrated error by integrating the VCO period normalized error T_pn.err; and

a quantizer configured to generate the ring oscillator control signal by mapping the integrated error to a control setting.

22. The re-circulating TDC of claim 21, wherein the quantizer is configured to truncate the least significant bits (LSB) of the integrated error.

23. An all-digital phase locked loop (ADPLL), comprising:

a digital phase/frequency detector configured to integrate frequency error by comparing a frequency word input to a differentiated TDC output in a feedback loop which is proportional to a frequency difference between the frequency word and the differentiated TDC output;

a digital loop filter configured to generate a filtered phase error signal by low-pass filtering the phase error signal;

a digital-to-analog converter (DAC) configured to convert the filtered phase error signal into a voltage input for a VCO;

the VCO configured to generate a periodic VCO signal at a specified frequency, wherein the voltage input is used to converge the VCO frequency to the specified frequency;

the re-circulating TDC of claim 18, configured to generate a TDC output signal from the VCO signal and the reference signal; and

a differenciator configured to generate the differentiated TDC output by differentiating the TDC output signal.

24. A method for time-to-digital conversion, comprising:

when triggered by a reference signal edge, clocking from a triggered reference ring oscillator a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period;

sampling a VCO signal clocked by the periodic ring oscillator signal;

storing the samples in a plurality of latches, wherein each latch is configured to store the sample for a different time interval; and

transmitting a digital state of the plurality of latches in parallel.

25. The method of claim 24, further comprising:

latching the digital state of the plurality of latches, including the samples of the VCO signal, after a sampling time interval, where the sampling time interval is a VCO period normalized time interval plus a state transition time interval, where the VCO period normalized time interval is substantially the TDC sample number times the VCO period, the TDC sample number is a positive integer of samples per VCO period, and the state transition time interval is a variable time interval after the VCO period normalized time interval when a specified latch transitions to a different digital state.

26. The method of claim 25, further comprising:

generating a TDC output from the latched the digital state, wherein the TDC output is a binary representation of a phase difference between a reference signal and the VCO signal; and

generating a ring oscillator control signal from the latched the digital state, wherein the ring oscillator control signal sets the ring oscillator period for the triggered reference ring oscillator.

27. The method of claim 24, further comprising:

stopping the clocking of the periodic ring oscillator signal when a specified latch from the plurality of latches transitions to a different digital state; and

resetting each latch of the plurality of latches to a predetermined state when the specified latch from the plurality of latches transitions to a different digital state.

28. The method of claim 24, wherein the ring oscillator period is substantially within one TDC sample width of a voltage-controlled oscillator (VCO) period, wherein the TDC sample width is one over a TDC sample number N_s times the VCO period, and the TDC sample number is a positive integer of samples per VCO period.

29. The method of claim 24, wherein the ring oscillator period is shorter than the VCO period and the ring oscillator period T_ref.ring is represented by (N_s−

1)/N_s*T_vco or the ring oscillator period is longer than the VCO period and the ring oscillator period T_ref.ring is represented by (N_s+1)/N_s*T_vco is the VCO period, N_s is a TDC sample number, and the TDC sample number is a positive integer of samples per the VCO period.

30. At least one non-transitory machine readable storage medium comprising a plurality of instructions adapted to be executed to implement the method according to claim 24.