Wafer examination device and wafer examination method

• US 9,201,094 B2
• Filed: 12/09/2013
• Issued: 12/01/2015
• Est. Priority Date: 12/10/2012
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Fujiwara, Hirokazu, Soejima, Narumasa
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Nguyen, Hoang X
• Application Number:
  US14/100,737
• Publication Number:
  US 20140159705A1
• Time in Patent Office: 722 Days
• Field of Search: 324/149, 324/754.01, 324/755.01, 324/757.03, 324/762.05, 438 17- 18, 438/661
• US Class Current: 1/1
• CPC Class Codes: G01N 27/20 Investigating the presence of flaws
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 1/067 Measuring probes
• CPC Class Codes: G01R 1/06755 Material aspects
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

A wafer examination device includes a probe, a fusion section and a measurement section. The probe is made of a metal which reacts with silicon carbide to produce silicide. The fusion section fuses the probe to a silicon carbide wafer as an examined object. The measurement section measures an electrical property of the silicon carbide wafer through the fused probe.

Claims

1. A wafer examination device, comprising:

a probe made of a metal which reacts with silicon carbide to produce silicide;

a fusion section which fuses the probe to a silicon carbide wafer as an examined object; and

a measurement section which measures an electrical property of the silicon carbide wafer through the fused probe.

2. The wafer examination device according to claim 1, wherein

the probe includes a core of silicon carbide and a coating material which contains the metal and is coated on the core, and

the metal includes at least one of nickel, titanium, aluminum, chromium, tantalum, molybdenum, tungsten, and cobalt.

3. The wafer examination device according to claim 1,

wherein the fusion section is an energizing device which applies current to the silicon carbide wafer through the probe.

4. The wafer examination device according to claim 3,

wherein the fusion section is configured to apply higher current to the probe than current which is applied to the probe when the electrical property is measured by the measurement section.

5. The wafer examination device according to claim 3,

wherein the fusion section is configured to apply an electric pulse to the probe at a higher voltage than a voltage at which the electric pulse is applied to the probe when the electrical property is measured by the measurement section.

6. A wafer examination method, comprising:

a fusion step of fusing a probe made of a metal which reacts with silicon carbide to produce suicide to a silicon carbide wafer as an examined object; and

an examination step of measuring an electrical property of the silicon carbide wafer through the fused probe.

7. The wafer examination method according to claim 6, further comprising:

a removal step of removing the fused probe and fused mark of the probe from the silicon carbide wafer,

wherein after the removal step, the fusion step and the examination step are again performed on the silicon carbide wafer whose electrical property has been measured.

8. The wafer examination method according to claim 6,

wherein the metal includes at least one of nickel, titanium, aluminum, chromium, tantalum, molybdenum, tungsten, and cobalt.

9. The wafer examination method according to claim 7,

wherein when the fusion step and the examination step are again performed, a position on which the probe is contacted is a same position as the fusion step previously performed.

10. The wafer examination method according to claim 7, further comprising:

an epilayer production step of producing an epitaxial layer on a surface layer of the silicon carbide wafer, the epitaxial layer having a thickness from 5 micrometers to 20 micrometers,

wherein in the removal step, the fused mark of the probe is removed together with the surface layer of the silicon carbide wafer.

11. The wafer examination method according to claim 6, further comprising:

an examined position determination step of determining, by examining presence or absence of a crystal defect in an epitaxial layer of the silicon carbide wafer prior to a first examination of the silicon carbide wafer, a position where no crystal defect is present as a position on which the probe is contacted.