Memory system

• US 9,201,717 B2
• Filed: 03/06/2014
• Issued: 12/01/2015
• Est. Priority Date: 03/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yano, Junji, Matsuzaki, Hidenori, Hatsuda, Kosuke
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US14/199,808
• Publication Number:
  US 20140189420A1
• Time in Patent Office: 635 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Claims

1. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a number of bad blocks in the nonvolatile memory, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory has reached a first threshold, a warning indication is issued,

in a case that the number of counted bad blocks in the nonvolatile memory has reached a second threshold, a data write operation to the nonvolatile memory is prohibited, the first threshold being less than the second threshold, wherein,

immediately after power is turned on and before the memory system is started, the controller inspects an internal state of the controller and refers to the number of counted bad blocks in the nonvolatile memory, and in a case that the number of counted bad blocks in the nonvolatile memory has reached the second threshold, the controller controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

2. The system according to claim 1, wherein, when an error occurs in the nonvolatile memory, the system shifts to a failure mode.

3. The system according to claim 1, wherein, when the system is powered on, the number of bad blocks is counted and compared with at least one of the first threshold and the second threshold.

4. The system according to claim 2, wherein, when the system shifts to the failure mode, the system displays an error message.

5. The system according to claim 1, further comprising a light emitting diode (an LED) indicating a status of the system.

6. The system according to claim 1, further comprising a temperature sensor monitoring a temperature of at least one of the nonvolatile memory and the controller.

7. The system according to claim 1, wherein, when the number of counted bad blocks is between the first threshold and the second threshold, data can be moved to backup.

8. The system according to claim 1, wherein, after the number of counted bad blocks has reached the second threshold, data can be moved to backup.

9. The system according to claim 2, wherein, after the system has shifted to the failure mode, data cannot be moved to backup.

10. The system according to claim 1, wherein logical addresses are translated to physical addresses of the nonvolatile memory.

11. A system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a reserve capacity in the nonvolatile memory, wherein,

in the case that the counted reserve capacity in the nonvolatile memory has reached a first threshold, a warning indication is issued,

after the counted reserve capacity in the nonvolatile memory has reached a second threshold, a data write operation to the nonvolatile memory is prohibited, the first threshold being less than the second threshold, wherein,

immediately after power is turned on and before the memory system is started, the controller inspects an internal state of the controller and refers to the counted reserve capacity in the nonvolatile memory,

in the case that the counted reserve capacity in the nonvolatile memory has reached the second threshold, the system controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

12. The system according to claim 11, wherein, when an error occurs in the nonvolatile memory, the system shifts to a failure mode.

13. The system according to claim 11, wherein, when the system is powered on, the reserve capacity is counted and compared with at least one of the first threshold and the second threshold.

14. The system according to claim 12, wherein, when the system shifts to the failure mode, the system displays an error message.

15. The system according to claim 11, further comprising a light emitting diode (an LED) indicating status of the system.

16. The system according to claim 11, further comprising a temperature sensor monitoring a temperature of at least one of the nonvolatile memory and the controller.

17. The system according to claim 11, wherein, when the counted reserve capacity is between the first threshold and the second threshold, data can be moved to backup.

18. The system according to claim 11, wherein, after the counted reserve capacity has reached the second threshold, data can be moved to backup.

19. The system according to claim 12, wherein, after the system has shifted to the failure mode, data cannot be moved to backup.

20. The system according to claim 11, wherein logical addresses are translated to physical addresses of the nonvolatile memory.

21. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a number of bad blocks in the nonvolatile memory, wherein,

in a case that the number of counted bad blocks has reached a first threshold, a warning indication is issued,

in a case that the number of counted bad blocks has reached a second threshold, the first threshold being less than the second threshold, wherein a data write operation to the nonvolatile memory is prohibited, and immediately after power is turned on and before the memory system is started, the controller inspects an internal state of the controller and refers to the number of counted bad blocks and controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

22. A system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a reserve capacity in the nonvolatile memory, wherein,

in the case that the counted reserve capacity in the nonvolatile memory has reached a first threshold, a warning indication is issued,

after the counted reserve capacity in the nonvolatile memory has reached a second threshold, a data write operation to the nonvolatile memory is prohibited, wherein,

immediately after power is turned on and before the memory system is started, the controller inspects an internal state of the controller and refers to the counted reserve capacity in the nonvolatile memory,

in the case that the counted reserve capacity in the nonvolatile memory has reached the second threshold, the system controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

23. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a number of bad blocks in the nonvolatile memory, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory has reached a threshold, a data write operation to the nonvolatile memory is prohibited, wherein,

after power is supplied from a host and the memory system is turned on, and before receiving a write command from the host, the controller refers to the number of counted bad blocks in the nonvolatile memory, and in a case that the number of counted bad blocks in the nonvolatile memory has reached the threshold, the controller controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

24. The system according to claim 23, wherein

the controller refers to the number of counted bad blocks in the nonvolatile memory before processing the write command from the host.

25. The system according to claim 23, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory exceeds a second threshold, the controller causes the host to issue a warning indication, the second threshold being less than the threshold.

26. The system according to claim 24, wherein

the controller includes a host interface circuit that receives the write command from the host.

27. The system according to claim 26, wherein

the nonvolatile memory is a NAND, and

the controller includes a NAND interface circuit that writes data in the NAND, and the controller checks, before the NAND interface circuit processes the write command, whether the NAND has been shifted to the read only mode in the past.

28. The system according to claim 26, wherein

the nonvolatile memory is a NAND, and

the controller writes data in the NAND in page units, and the controller erases data from the NAND in block units.

29. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a number of bad blocks in the nonvolatile memory, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory has reached a threshold, a data write operation to the nonvolatile memory is prohibited, wherein,

after the memory system is restarted and before receiving a write command from a host, the controller refers to the number of counted bad blocks in the nonvolatile memory, and in a case that the number of counted bad blocks in the nonvolatile memory has reached the threshold, the controller controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

30. The system according to claim 29, wherein

the controller refers to the number of counted bad blocks in the nonvolatile memory before processing the write command from the host.

31. The system according to claim 29, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory exceeds a second threshold, the controller causes the host to issue a warning indication, the second threshold being less than the threshold.

32. The system according to claim 30, wherein

the controller includes a host interface circuit that receives the write command from the host.

33. The system according to claim 32, wherein

the nonvolatile memory is a NAND, and

the controller includes a NAND interface circuit that writes data in the NAND, and the controller checks, before the NAND interface circuit processes the write command, whether the NAND has been shifted to the read only mode in the past.

34. The system according to claim 32, wherein

the nonvolatile memory is a NAND, and

the controller writes data in the NAND in page units, and the controller erases data from the NAND in block units.

35. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to count a number of bad blocks in the nonvolatile memory, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory has reached a threshold, a warning indication is issued, and after the warning is issued, a data write operation to the nonvolatile memory is prohibited, wherein,

after restarting power supply from a host, the controller refers to the number of counted bad blocks in the nonvolatile memory, and in a case that the number of counted bad blocks in the nonvolatile memory has reached the threshold, the controller controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

36. The system according to claim 35, wherein

the controller refers to the number of counted bad blocks in the nonvolatile memory before processing a write command from the host.

37. The system according to claim 35, wherein,

in a case that the number of counted bad blocks in the nonvolatile memory exceeds a second threshold, the controller causes the host to issue a warning indication, the second threshold being less than the threshold.

38. The system according to claim 36, wherein

the controller includes a host interface circuit that receives the write command from the host.

39. The system according to claim 38, wherein

the nonvolatile memory is a NAND, and

the controller includes a NAND interface circuit that writes data in the NAND, and the controller checks, before the NAND interface circuit processes the write command, whether the NAND has been shifted to the read only mode in the past.

40. The system according to claim 38, wherein

the nonvolatile memory is a NAND, and

the controller writes data in the NAND in page units, and the controller erases data from the NAND in block units.

41. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to refer a number of errors in the nonvolatile memory, wherein,

in a case that the number of the errors in the nonvolatile memory has reached a threshold, a warning indication is issued, and after the warning is issued, a data write operation to the nonvolatile memory is prohibited, wherein,

after restarting power supply from a host and the memory system is turned on, and before receiving a write command from the host, the controller controls the nonvolatile memory so that the nonvolatile memory is started in a read only mode.

42. The system according to claim 41, wherein

the error is an error in a case that an erasing operation failed.

43. The system according to claim 42, wherein

the controller refers to the number of errors in the nonvolatile memory before processing the write command from the host.

44. The system according to claim 42, wherein,

in a case that the number of errors in the nonvolatile memory exceeds a second threshold, the controller causes the host to issue a warning indication, the second threshold being less than the threshold.

45. The system according to claim 43, wherein

the controller includes a host interface circuit that receives the write command from the host.

46. The system according to claim 45, wherein

the nonvolatile memory is a NAND, and

the controller includes a NAND interface circuit that writes data in the NAND, and the controller checks, before the NAND interface circuit processes the write command, whether the NAND has been shifted to the read only mode in the past.

47. The system according to claim 45, wherein

the nonvolatile memory is a NAND, and

the controller writes data in the NAND in page units, and the controller erases data from the NAND in block units.