System-on-chip and method for sending data in a system-on-chip

• US 9,201,722 B1
• Filed: 07/10/2014
• Issued: 12/01/2015
• Est. Priority Date: 07/10/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moeller, Dirk, Limmer, Peter Ludwig, Roettgermann, Clemens Alfred
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US14/327,675
• Time in Patent Office: 509 Days
• Field of Search: 714/819, 714/821, 714/749, 714/748, 714/751, 377/28, 377/30, 377/31, 377/39, 377/107
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06M 3/08 for counting the input from several sources; for counting inputs of different amounts
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/1685 the supervisory signal being transmitted in response to a specific request, e.g. to a polling signal

Abstract

A system-on-chip comprising a sender unit and a receiver unit and a method of operating thereof are described. The sender unit comprises a send counter for providing a send counter value. The receiver unit comprises a receive counter for providing a receive counter value. The sender unit is arranged to increment the send counter value by an increment and send a data packet to the receiver unit. The receiver unit is arranged to receive the data packet and increment the receive counter value by the increment. In a challenge operation, the sender unit sends the send counter value to the receiver unit. In a challenge response operation, the receiver unit receives the send counter value, compares the values, and generates a comparison result. Loss of data packets from the sender unit as well as reception of unexpected data packets from a third functional unit may thus be detected.

Claims

1. A system-on-chip, SoC, comprising a sender unit and a receiver unit, wherein

the sender unit comprises a send counter for providing a send counter value;

the receiver unit comprises a receive counter for providing a receive counter value;

the sender unit is arranged to perform a send operation, wherein the send operation comprises incrementing the send counter value by an increment and sending a data packet to the receiver unit; and

the receiver unit is arranged to perform a receive operation in response to the send operation, wherein the receive operation comprises receiving the data packet and incrementing the receive counter value by the increment;

the sender unit is arranged to perform a challenge operation, wherein the challenge operation comprises sending the send counter value to the receiver unit; and

the receiver unit is arranged to perform a challenge response operation in response to the challenge operation, wherein the challenge response operation comprises;

receiving the send counter value, comparing the send counter value against the receive counter value, and generating a comparison result which is indicative of whether or not the receive counter value and the send counter value are identical.

2. The system-on-chip of claim 1, arranged to set the send counter value and the receive counter value to a common initial value in response to a counter initialization signal.

3. The system-on-chip of claim 1, wherein

the sender unit is arranged to perform an initialization operation which comprises sending the send counter value to the receiver unit and

the receiver unit is arranged to perform an initialization response operation in response to the initialization operation, wherein the initialization response operation comprises setting the receive counter value to the send counter value.

4. The system-on-chip of claim 1, wherein the send counter and the receive counter are wrap-around counters and have a same maximum count.

5. The system-on-chip of claim 1, wherein the sender unit is arranged to perform the challenge operation in response to a critical number reaching a challenge-triggering data packet number, wherein the critical number is a number of data packets sent by the sender unit to the receiver unit since a preceding challenge operation.

6. The system-on-chip of claim 5, wherein the challenge-triggering data packet number is programmable.

7. The system-on-chip of claim 5, wherein the challenge-triggering data packet number is greater or equal two.

8. The system-on-chip of claim 1, wherein the sender unit is arranged perform the challenge operation in response to a number of clock cycles since a preceding challenge operation reaching a challenge-triggering clock cycle number.

9. The system-on-chip of claim 1, wherein the sender unit is a central processing unit or an instance of a program executed by a central processing unit, and the receiver unit is an integrated peripheral.

10. A method for sending data from a sender unit to a receiver unit, comprising:

operating a send counter in the sender unit to provide a send counter value;

operating a receive counter in the receiver unit to provide a receive counter value;

operating the sender unit to perform a send operation, wherein the send operation comprises incrementing the send counter value by an increment and sending a data packet to the receiver unit;

in response to the send operation, operating the receiver unit to perform a receive operation, wherein the receive operation comprises receiving the data packet and incrementing the receive counter value by the increment;

operating the sender unit to perform a challenge operation, wherein the challenge operation comprises sending the send counter value to the receiver unit; and

in response to the challenge operation, operating the receiver unit to perform a challenge response operation, wherein the challenge response operation comprises;

receiving the send counter value, comparing the send counter value against the receive counter value, and generating a comparison result which is indicative of whether or not the receive counter value and the send counter value are identical.