Systems and methods for soft data utilization in a solid state memory system

• US 9,201,729 B2
• Filed: 11/05/2013
• Issued: 12/01/2015
• Est. Priority Date: 10/21/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Wu, Yunxiang, Cai, Yu, Haratsch, Erich F.
• Primary Examiner(s): Ton, David
• Application Number:
  US14/072,574
• Publication Number:
  US 20150113318A1
• Time in Patent Office: 756 Days
• Field of Search: 714/780
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.

Claims

1. A data processing system, the system comprising:

a soft data modification circuit operable to apply a transfer function to an original soft data corresponding to the data set accessed from a solid state memory device to yield a modified soft data set; and

a data decoder circuit operable to apply one or more iterations of a data decoding algorithm to the data set accessed from the solid state memory device to yield a decoded output based at least in part on the modified soft data.

2. The data processing system of claim 1, wherein the data decoding algorithm is a low density parity check decoding algorithm.

3. The data processing system of claim 1, wherein the transfer function is a non-uniform transfer function.

4. The data processing system of claim 3, wherein the non-uniform transfer function is operable to decrease a probability indicated by a first portion of the original soft data, and to increase a probability indicating by a second portion of the original soft data.

5. The data processing system of claim 4, wherein the first portion of the original soft data exhibits a lower probability than the second portion of the original soft data.

6. The data processing system of claim 1, wherein the original soft data includes a first number of bits per element, wherein the modified soft data set includes a second number of bits per element, wherein the transfer function is a non-uniform transfer function that is applied to yield an interim data set, and wherein the soft data modification circuit is further operable to force the value of any element of the interim data set that falls outside of a range of the second number of bits per element to equal the nearest extreme of the range to yield the modified soft data set.

7. The data processing system of claim 1, wherein the data processing system is implemented in an integrated circuit.

8. The data processing system of claim 1, wherein the data processing system further comprises:

the solid state memory device operable to maintain the data set; and

wherein the data processing system including the solid state memory device is implemented on an integrated circuit.

9. The data processing system of claim 8, wherein the solid state memory device is a flash memory device.

10. The data processing system of claim 9, wherein the flash memory device is able to hold multiple bits of data in each memory cell of the flash memory device.

11. The data processing system of claim 1, wherein the system further comprises:

a soft data generation circuit operable to generate the original soft data.

12. A method for recovering data from a memory, the method comprising:

receiving a data set from a memory device;

applying a transfer function to an original soft data corresponding to the data set accessed from a memory device to yield a modified soft data set; and

applying at least one iteration of a data decoding algorithm to the modified soft data set using a data decoding circuit to yield a decoded output.

13. The method of claim 12, wherein the data decoding algorithm is a low density parity check decoding algorithm.

14. The method of claim 12, wherein the transfer function is a non-uniform transfer function.

15. The method of claim 14, wherein the non-uniform transfer function is operable to decrease a probability indicated by a first portion of the original soft data, and to increase a probability indicating by a second portion of the original soft data.

16. The method of claim 15, wherein the first portion of the original soft data exhibits a lower probability than the second portion of the original soft data.

17. The method of claim 12, wherein the original soft data includes a first number of bits per element, wherein the modified soft data set includes a second number of bits per element, wherein the transfer function is a non-uniform transfer function that is applied to yield an interim data set, and wherein applying the non-uniform transfer function to the original soft data yield a modified soft data set includes:

applying the applying the non-uniform transfer function to the original soft data yields an interim data set; and

forcing any element of the interim data set that falls outside of a range of the second number of bits per element to equal the nearest extreme of the range to yield the modified soft data set.

18. The method of claim 12, wherein the memory device is a flash memory device.

19. The method of claim 18, wherein the flash memory device is able to hold multiple bits of data in each memory cell of the flash memory device.

20. A memory system comprising:

a solid state memory device operable to maintain a data set;

a soft data generation circuit operable to generate original soft data corresponding to the data set;

a soft data modification circuit operable to apply a transfer function to an original soft data corresponding to the data set accessed from a memory device to yield a modified soft data set; and

a data decoder circuit operable to apply one or more iterations of a data decoding algorithm to the data set accessed from the memory device to yield a decoded output based at least in part on the modified soft data.