Integrated circuit and method for monitoring bus status in integrated circuit
First Claim
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1. An integrated circuit, comprising:
- a processor, a host bus, multiple branch buses, multiple status detectors, a top layer monitor, and an interface;
whereinthe multiple branch buses are coupled to the processor through the host bus;
the host bus is configured to transmit data from the multiple branch buses to the processor;
the processor is configured to perform data processing;
each status detector in the multiple status detectors is coupled to a respective, corresponding branch bus in the multiple branch buses, and is configured to read status data on the corresponding branch bus that is coupled to the status detector, and upload the status data to the top layer monitor; and
the top layer monitor is configured to collect the status data from each status detector, and output the status data through the interface, wherein the status data collected by each status detector reflects a status condition of the corresponding branch bus, the status condition corresponding to a volume of data that the corresponding branch bus bears.
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Abstract
Embodiments of the present invention disclose an integrated circuit and a method for monitoring a bus status in the integrated circuit. Multiple status detectors and a top layer monitor are disposed in the integrated circuit. Each status detector in the multiple status detectors is used to read status data on a branch bus that is coupled to each status detector in the multiple status detectors, and then the top layer monitor collects the status data from each status detector, and outputs the status data through an interface.
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Citations
14 Claims
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1. An integrated circuit, comprising:
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a processor, a host bus, multiple branch buses, multiple status detectors, a top layer monitor, and an interface;
whereinthe multiple branch buses are coupled to the processor through the host bus; the host bus is configured to transmit data from the multiple branch buses to the processor; the processor is configured to perform data processing; each status detector in the multiple status detectors is coupled to a respective, corresponding branch bus in the multiple branch buses, and is configured to read status data on the corresponding branch bus that is coupled to the status detector, and upload the status data to the top layer monitor; and the top layer monitor is configured to collect the status data from each status detector, and output the status data through the interface, wherein the status data collected by each status detector reflects a status condition of the corresponding branch bus, the status condition corresponding to a volume of data that the corresponding branch bus bears. - View Dependent Claims (2, 3, 4, 5, 6, 7, 11, 12)
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8. A method for monitoring a bus status in an integrated circuit, comprising:
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reading, by each status detector in multiple status detectors, status data on a respective, corresponding branch bus in multiple branch buses that is coupled to the status detector; and collecting, by a top layer monitor, the status data from each status detector, and outputting the status data through an interface, wherein the status data collected from each status detector reflects a status condition of the corresponding branch bus, the status condition corresponding to a volume of data that the corresponding branch bus bears, wherein the branch buses are coupled to a processor through a host bus; the host bus is configured to transmit data from the branch buses to the processor; and the processor is configured to perform data processing. - View Dependent Claims (9, 10, 13, 14)
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Specification