Quality of service support using stacked memory device with logic die

• US 9,201,777 B2
• Filed: 12/23/2012
• Issued: 12/01/2015
• Est. Priority Date: 12/23/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hsu, Lisa R., Loh, Gabriel H., Beckmann, Bradford M., Ignatowski, Michael
• Primary Examiner(s): NGUYEN, HIEP T
• Application Number:
  US13/726,144
• Publication Number:
  US 20140181428A1
• Time in Patent Office: 1,073 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware.

Claims

1. An integrated circuit (IC) device comprising:

a set of one or more stacked memory dies implementing memory cell circuitry; and

a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies comprising a quality-of-service (QoS) manager and a memory controller, the memory controller coupled to the QoS manager and coupleable to a set of one or more devices sharing access to the set of one or more stacked memory dies, and the QoS manager to perform operations for a specified QoS objective.

2. The IC device of claim 1, further comprising:

a storage array to store QoS tracking metadata representing memory utilization metrics for the set of one or more stacked memory dies; and

wherein the QoS manager is to monitor the memory controller to update the QoS tracking metadata responsive to memory access requests serviced by the memory controller.

3. The IC device of claim 2, wherein:

the specified QoS objective comprises maintaining the QoS tracking metadata on behalf of a select device of the set of one or more devices; and

the QoS manager is to perform an operation to transmit at least a portion of the QoS tracking metadata to the select device responsive to a request received from the select device.

4. The IC device of claim 2, wherein the QoS tracking metadata includes at least one of:

a bandwidth metric on at least one of a per-sharer basis, a per-sharer-class basis, a per-device basis, a per-device-class basis, a per-interface basis, and a per-access-type basis;

a latency metric on at least one of a per-sharer basis, a per-sharer-class basis, a per-device basis, a per-device-class basis, a per-interface basis, and a per-access-type basis; and

a power consumption metric on at least one of a per-sharer basis, a per-sharer-class basis, a per-device basis, a per-device-class basis, a per-interface basis, and a per-access-type basis.

5. The IC device of claim 1, wherein the QoS manager is to arbitrate access to the set of one or more stacked memory dies among sharers of the set of one or more stacked memory dies based on the specified QoS objective.

6. The IC device of claim 5, wherein the specified QoS objective comprises at least one of:

an equal bandwidth allocation among at least a subset of the sharers;

a minimum bandwidth for a subset of the sharers;

a minimum average access latency for at least a subset of the sharers;

a maximum access throughput for at least a subset of the sharers;

a maximum access latency for a subset of the sharers; and

an equal power consumption among at least a subset of the sharers.

7. The IC device of claim 5, wherein the specified QoS objective comprises at least one of:

a minimum bandwidth for a specified type of memory access;

a minimum average access latency for a specified type of memory access;

a maximum access throughput for a specified type of memory access; and

a maximum access latency for a specified type of memory access.

8. The IC device of claim 5, wherein the QoS manager is to arbitrate access by managing an order of memory access requests to be serviced by the memory controller.

9. The IC device of claim 5, wherein the QoS manager is to arbitrate access through selective rejection of memory access requests from the set of devices.

10. The IC device of claim 5, wherein the QoS manager is to arbitrate access by managing an order in which memory access results are returned to the sharers.

11. The IC device of claim 5, wherein the QoS manager is to arbitrate access by selectively reserving resources of the IC device for use in servicing memory access requests.

12. The IC device of claim 5, wherein the QoS manager comprises:

a multiplexer having a plurality of memory access request inputs, an output, and a selection input, each memory access request input coupled to an output of a corresponding memory access request queue of a plurality of memory access request queues, and the output coupled to an input of the memory controller; and

arbitration logic having an input to receive queue status information for each memory access request queue, an input to receive QoS tracking metadata representing a memory utilization history for the sharers, an input to receive control data representative of the specified QoS objective, and an output coupled to the selection input of the multiplexer, wherein the arbitration logic is to configure its output to control the multiplexer to provide a memory access request from a selected one of the plurality of memory access request queues to the memory controller for servicing, the selected one of the plurality of memory access request queues selected based at least in part on the queue status information, the QoS tracking metadata, and the specified QoS objective.

13. The IC device of claim 1, wherein the set of one or more stacked memory dies and the set of one or more logic dies are disposed in a stacked configuration whereby the memory controller is connected to the stacked memory dies via a set of through silicon vias.

14. The IC device of claim 1, wherein the set of one or more stacked memory dies and the set of one or more logic dies are disposed in a side-split arrangement whereby the memory controller is connected to the set of one or more stacked memory dies via an interposer.

15. A method comprising:

operating an integrated circuit (IC) device to perform memory access requests for one or more devices of a set of devices external to the IC device, the IC device comprising a set of one or more stacked memory dies comprising memory cell circuitry and comprising a set of one or more logic dies electrically coupled to the set of one or more stacked memory dies, the set of one or more logic dies comprising a quality of service (QoS) manager coupled to the memory cell circuitry of the set of one or more stacked memory dies and comprising a memory controller coupled to the QoS manager and coupled to the one or more devices; and

operating the QoS manager to perform operations for a specified QoS objective.

16. The method of claim 15, wherein operating the QoS manager comprises operating the QoS manager to arbitrate access to the set of one or more stacked memory dies among sharers of the set of one or more stacked memory dies based on the specified QoS objective.

17. The method of claim 16, wherein operating the QoS manager to arbitrate access comprises operating the QoS manager to arbitrate access by managing an order of memory access requests to be serviced by the memory controller.

18. The method of claim 16, wherein operating the QoS manager to arbitrate access comprises operating the QoS manager to arbitrate access through selective rejection of memory access requests from the set of devices.

19. The method of claim 16, wherein operating the QoS manager to arbitrate access comprises operating the QoS manager to arbitrate access by managing an order in which memory access results are returned to the sharers.

20. The method of claim 16, wherein operating the QoS manager to arbitrate access comprises operating the QoS manager to arbitrate access by selectively reserving resources of the IC device for use in servicing memory access requests.

21. The method of claim 16, further comprising:

operating a plurality of memory access request queues to receive a plurality of memory access requests;

operating a multiplexer of the IC device to select between the plurality of memory access request queues for output to an input of the memory controller; and

operating arbitration logic of the IC device to control the multiplexer to output a memory access request from a selected one of the plurality of memory access request queues to the memory controller for servicing, the selected one of the plurality of memory access request queues selected based at least in part on queue status information for each of the plurality of memory access request queues, the QoS tracking metadata representing a memory utilization history for the sharers, and the specified QoS objective.

22. A non-transitory computer readable medium storing code which is operable to manipulate at least one computer system to perform a portion of a process to fabricate an integrated circuit (IC) device, the IC device comprising:

a set of one or more stacked memory dies implementing memory cell circuitry; and

a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies comprising a quality-of-service (QoS) manager and a memory controller, the memory controller coupled to the QoS manager and coupleable to a set of one or more devices sharing access to the set of one or more stacked memory dies, and the QoS manager to perform operations for a specified QoS objective.

23. The non-transitory computer readable medium of claim 22, wherein the IC device further comprises:

a storage array to store QoS tracking metadata representing memory utilization metrics for the set of one or more stacked memory dies; and

wherein the QoS manager is to monitor the memory controller to update the QoS tracking metadata responsive to memory access requests serviced by the memory controller.

24. The non-transitory computer readable medium of claim 22, wherein the QoS manager is to arbitrate access to the set of one or more stacked memory dies among sharers of the set of one or more stacked memory dies based on the specified QoS objective.