In-situ block folding for nonvolatile memory

• US 9,201,788 B1
• Filed: 10/22/2014
• Issued: 12/01/2015
• Est. Priority Date: 05/15/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Avila, Chris, Dusija, Gautam, Raghu, Deepak, Hsu, Cynthia, Chen, Changyuan, Moogat, Farookh
• Primary Examiner(s): SCHNEE, HAL W
• Application Number:
  US14/520,909
• Publication Number:
  US 20150331626A1
• Time in Patent Office: 405 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Claims

1. A method of operating a Multi-Level Cell (MLC) nonvolatile memory array that stores more than two bits per page, comprising:

programming a first logical page of data one-bit-per-cell in a first physical page using a first programming scheme;

programming a second logical page of data one-bit-per-cell in a second physical page using a second programming scheme;

programming a third logical page of data one-bit-per-cell in a third physical page using the second programming scheme;

subsequently, copying the second and third logical pages of data to the first physical page where they are programmed with the first logical page; and

marking the second physical page and the third physical page as obsolete.

2. The method of claim 1 further comprising, maintaining the first logical page of data in Dynamic Random Access Memory (DRAM) during the copying of the second and third logical pages of data to the first physical page.

3. The method of claim 1 wherein the first physical page is in a first block that comprises a plurality of physical pages and all of the plurality of physical pages of the first block are programmed one-bit-per-cell prior to the copying.

4. The method of claim 3 wherein the second physical page is in a second block, the third physical page is in a third block, and the second and third blocks have all physical pages programmed one-bit-per-cell prior to the copying.

5. The method of claim 3 wherein one or more additional copying steps directed to additional physical pages of the plurality of physical pages of the first block are performed between copying the second logical page of data to the first physical page and copying the third logical page of data to the first physical page.

6. The method of claim 5 further comprising maintaining one-bit-per-cell data from each individual physical page of the plurality of physical pages of the first block in DRAM for a time during which additional bits are copied to cells of the plurality of physical pages.

7. The method of claim 6 further comprising performing foggy programming and subsequently performing fine programming when copying, and maintaining one-bit-per-cell data of an individual physical page until after completion of fine programming of the individual physical page.

8. The method of claim 1 wherein the MLC nonvolatile memory array is a three dimensional nonvolatile memory array.

9. The method of claim 1 wherein the first programming scheme is an MLC lower page programming scheme, and the second programming scheme is an SLC scheme.

10. The method of claim 1 wherein the first programming scheme programs memory cell threshold voltages to a first threshold voltage range, the second programming scheme programs memory cell threshold voltages to a second threshold voltage range, the second threshold voltage range being higher than the first threshold voltage range.

11. A block-erasable nonvolatile memory system comprising:

a plurality of Single Level Cell (SLC) blocks that store one bit per cell;

a plurality of Multi Level Cell (MLC) blocks that store three or more bits per cell; and

a plurality of hybrid blocks that initially store data using only one bit per cell in cells of three or more word lines and are subsequently further programmed to store two or more additional bits per cell in the cells of the three or more word lines.

12. The block-erasable nonvolatile memory system of claim 11 further comprising a Dynamic Random Access Memory (DRAM) that stores a copy of data initially stored in a hybrid block during subsequent further programming of the hybrid block.

13. The block-erasable nonvolatile memory system of claim 11 wherein a hybrid block initially stores one bit per cell in cells of substantially all word lines of the hybrid block.

14. The block-erasable nonvolatile memory system of claim 11 further comprising a copying circuit that copies data from two or more SLC blocks to a hybrid block that contains one bit per cell.

15. The block-erasable nonvolatile memory system of claim 11 further comprising programming circuits that program SLC blocks using an SLC programming scheme and program initial one-bit-per-cell data in hybrid blocks using a lower page MLC programming scheme that is different to the SLC programming scheme.

16. A block-erasable nonvolatile memory system comprising:

a plurality of Single Level Cell (SLC) blocks that store one bit per cell;

a plurality of Multi Level Cell (MLC) blocks that store three or more bits per cell;

a plurality of hybrid blocks, an individual hybrid block configured to initially store data using only one bit per cell in at least cells of a first word line, cells of a second word line, and cells of a third word line that are subsequently further programmed with data copied from two or more SLC blocks to store two or more additional bits per cell in the cells of the first, second, and third word lines; and

a Random Access Memory (RAM) that is configured to maintain a safe copy of the data that was initially stored in the cells of the first, second, and third word lines during subsequent further programming with the data copied from the two or more SLC blocks.

17. The block-erasable nonvolatile memory system of claim 16 further comprising:

a memory controller configured to select a write mode for data to be written in the memory system from a plurality of write modes that includes a hybrid write mode that initially stores some data of a write command in SLC blocks and stores other data of the write command in at least one hybrid block.

18. The block-erasable nonvolatile memory system of claim 17 wherein the plurality of write modes further includes an SLC write mode that stores all data of a write command in SLC blocks.

19. The block-erasable nonvolatile memory system of claim 18 wherein the plurality of write modes further includes an MLC write mode that stores all data of a write command in one or more MLC blocks without previously storing the data of the write command in SLC blocks.

20. The block-erasable nonvolatile memory system of claim 16 further comprising write circuits configured to program data in SLC blocks using an SLC programming scheme and configured to program one bit per cell in hybrid blocks using an MLC lower page programming scheme that is different to the SLC programming scheme.