Command processing apparatus, method and integrated circuit apparatus
First Claim
1. A command processing apparatus, comprising:
- a command processor that includes a plurality of buffers, the plurality of buffers obtaining commands which are issued asynchronously from a first master and a second master, the command processor processing and sequentially issuing the commands to a storage apparatus including a plurality of banks,wherein, when the first master requests consecutive selection and issues a first command and a second command to one of the plurality of buffers, and the second master issues a third command to another of the plurality of buffers, the command processor consecutively issues the first command to the storage apparatus and the second command to the storage apparatus, andthe consecutive selection request by the first master requests consecutive issuance of the first command and the second command to the storage apparatus.
3 Assignments
0 Petitions
Accused Products
Abstract
A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
17 Citations
20 Claims
-
1. A command processing apparatus, comprising:
-
a command processor that includes a plurality of buffers, the plurality of buffers obtaining commands which are issued asynchronously from a first master and a second master, the command processor processing and sequentially issuing the commands to a storage apparatus including a plurality of banks, wherein, when the first master requests consecutive selection and issues a first command and a second command to one of the plurality of buffers, and the second master issues a third command to another of the plurality of buffers, the command processor consecutively issues the first command to the storage apparatus and the second command to the storage apparatus, and the consecutive selection request by the first master requests consecutive issuance of the first command and the second command to the storage apparatus. - View Dependent Claims (2, 3, 4, 5, 10, 12, 14, 15, 16)
-
-
6. A command processing apparatus, comprising:
-
a command processor that includes a plurality of buffers, the plurality of buffers obtaining commands which are issued asynchronously from a first master and a second master, the command processor processing and sequentially issuing the commands to a storage apparatus including a plurality of banks, wherein, when the first master requests consecutive selection and issues a first command and a second command to one of the plurality of buffers, and the second master issues a third command to another of the plurality of buffers, the command processor performs one of the following;
consecutively issuing the first command to the storage apparatus and the second command to the storage apparatus and subsequently issuing the third command to the storage apparatus; and
issuing the third command to the storage apparatus and subsequently consecutively issuing the first command to the storage apparatus and the second command to the storage apparatus, andthe consecutive selection request by the first master requests consecutive issuance of the first command and the second command to the storage apparatus. - View Dependent Claims (7, 8, 9, 11, 13, 17, 18, 19)
-
-
20. A command processing apparatus, comprising:
-
a plurality of buffers that obtains commands which are issued asynchronously from a plurality of masters; an arbitrator that reads the commands from the plurality of buffers and arbitrates the commands for sequential issuance to a storage; wherein the arbitrator consecutively obtains and issues a first command and a second command from one of the plurality of buffers in response to receiving a consecutive selection request signal, the consecutive selection request signal being received by the arbitrator in association with the first command, the first command and the second command each being obtained by the one of the plurality of buffers from a first master of the plurality of masters.
-
Specification