Integrated circuit floorplan having feedthrough buffers

• US 9,201,999 B1
• Filed: 09/30/2014
• Issued: 12/01/2015
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Sahni, Prakash
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/501,462
• Time in Patent Office: 427 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method and a system are provided for planning feedthrough ports on a floorplan for an integrated circuit. In one example, the system groups paths (e.g., nets) into mutually exclusive families of paths (e.g., nets). The system analyzes the simpler path combinations for each path family. Advantageously, the system can find consistent design solutions for paths (e.g., nets), while adding fewer ports and fewer nets, within a practical amount of time.

Claims

1. A method of generating design data for an integrated circuit, the method comprising:

identifying one or more driver-sink pairs on instantiations of modules, wherein the modules include a driver module, an intermediate module, and a sink module;

for a first set of instantiations, generating a first path that extends from a driver instantiation (A1), across an intermediate instantiation (B1), to a sink instantiation (C1);

for a second set of instantiations, generating a second path that extends from the driver instantiation (A2), across the intermediate instantiation (B2), to the sink instantiation (C2); and

determining that the first path and the second path cross at an identical input location on the intermediate instantiations;

in response to the identical input location, generating a first input port on the intermediate module, wherein the first input port on the intermediate module is assigned a first family identifier and a first input port location, the first input port and the first input port location defining design data; and

generating a photomask for the integrated circuit from the design data.

2. The method of claim 1, wherein the generating of the first input port is performed before physically designing at least one of the driver module, the intermediate module, or the sink module.

3. The method of claim 1, further comprising:

planning to connect a first output port of the driver module to the first input port on the intermediate module by way of a channel-less electrical connection.

4. The method of claim 1, further comprising:

for the first set of instantiations, generating a third path that extends from the driver module (A1), across a second intermediate module (D1), to a sink module (C1);

for the second set of instantiations, generating a fourth path that extends from the driver module (A2), across the second intermediate module (D2), to the sink module (C2);

determining that the third path or the fourth path is associated with a routing blockage; and

in response to the routing blockage, deciding not to use the third path or the fourth path for the floorplan.

5. The method of claim 4, further comprising:

backtracking to continue using the first path and the second path for the floorplan, instead using of the third path and the fourth path for the floorplan.

6. A system for generating design data for an integrated circuit, the system comprising:

a processor to execute instructions; and

a storage device coupled to the processor, the storage device storing instructions for execution by the processor to cause the processor to perform;

identifying one or more driver-sink pairs on instantiations of modules, wherein the modules include a driver module, an intermediate module, and a sink module;

for a first set of instantiations, generating a first path that extends from a driver instantiation (A1), across an intermediate instantiation (B1), to a sink instantiation (C1);

for a second set of instantiations, generating a second path that extends from the driver instantiation (A2), across the intermediate instantiation (B2), to the sink instantiation (C2);

determining that the first path and the second path cross at an identical input location on the intermediate instantiations;

in response to the identical input location, generating a first input port on the intermediate module, wherein the first input port on the intermediate module is assigned a first family identifier and a first input port location, the first input port and the first input port location defining design data; and

generating a photomask for the integrated circuit from the design data.

7. The system of claim 6, wherein:

the first path is represented by a first air-line; and

the second path is represented by a second air-line.

8. The system of claim 6, wherein:

for the first set of a instantiations, the first path extends from a center of the driver instantiation (A1) to a center of the sink instantiation (C1); and

for the second set of instantiations, the second path extends from a center of the driver instantiation (A2) to a center of the sink instantiation (C2).

9. The system of claim 6, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

determining that the first path and the second path cross at an identical output location on the intermediate instantiations; and

in response to the identical output location, generating an output port on the intermediate module, wherein the output port on the intermediate module is assigned the first family identifier and a first output port location.

10. The system of claim 9, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

generating a first feedthrough buffer for the intermediate module, wherein the first feedthrough buffer extends from the first input port on the intermediate module to the first output port on the intermediate module.

11. The system of claim 9, wherein the storage device stores further instructions or execution by the processor to cause the processor to perform:

planning for the first feedthrough buffer to be physically identical on all instantiations of the intermediate module; and

assigning a different identifier to the first feedthrough buffer for each instantiation of the intermediate module.

12. The system of claim 6, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

determining that the first path and the second path cross at different output locations on the intermediate module (B1) and the intermediate module (B2); and

generating different output ports for the different output locations on the intermediate module.

13. The system of claim 6, wherein the generating the first input port further comprises:

modifying a hardware description language (HDL) of a netlist of the floorplan.

14. The system of claim 6, wherein the generating of the first input port is performed before physically designing at least one of the driver module, the intermediate module, or the sink module.

15. The system of claim 6, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

planning to connect a first output port of the driver module to the first input port on the intermediate module by way of a channel-less electrical connection.

16. The system of claim 6, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

for the first set of instantiations, generating a third path that extends from the driver module (A1), across a second intermediate module (D1), to a sink module (C1);

for the second set of instantiations, generating a fourth path that extends from the driver module (A2), across the second intermediate module (D2), to the sink module (C2);

determining that the third path or the fourth path is associated with a routing blockage; and

in response to the routing blockage, deciding not to use the third path or the fourth path for the floorplan.

17. The system of claim 16, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

backtracking to continue using the first path and the second path for the floorplan, instead using of the third path and the fourth path for the floorplan.

18. The system of claim 6, wherein the storage device stores further instructions for execution by the processor to cause the processor to perform:

for a third set of instantiations, determining that a path combination between a driver and two different sinks requires an output port of the driver to be split; and

deciding not to use the path combination that requires the output port of the driver to be split.

19. A computer-readable product for generating design data for an integrated circuit, the computer-readable product including a non-transitory computer-readable storage medium storing instructions comprising:

identifying one or more driver-sink pairs on instantiations of modules, wherein the modules include a driver module, an intermediate module, and a sink module;

for a first set of instantiations, generating a first path that extends from a driver instantiation (A1), across an intermediate instantiation (B1), to a sink instantiation (C1);

for a second set of instantiations, generating a second path that extends from the driver instantiation (A2), across the intermediate instantiation (B2), to the sink instantiation (C2);

determining that the first path and the second path cross at an identical input location on the intermediate instantiations;

in response to the identical input location, generating a first input port on the intermediate module, wherein the first input port on the intermediate module is assigned a first family identifier and a first input port location, the first input port and the first input port location defining design data; and

generating a photomask for the integrated circuit from the design data.

20. The computer-readable product of claim 19, wherein the instructions stored on the storage device further comprise:

determining that the first path and the second path cross at an identical output location on the intermediate instantiations; and

in response to the identical output location, generating an output port on the intermediate module, wherein the output port on the intermediate module is assigned the first family identifier and a first output port location.