Wordline activation

• US 9,202,538 B2
• Filed: 12/05/2013
• Issued: 12/01/2015
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lehmann, Gunther, Gupta, Siddharth
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/097,425
• Publication Number:
  US 20150162056A1
• Time in Patent Office: 726 Days
• Field of Search: 365/154, 365/155, 365/156, 365/189.08
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Methods and devices are disclosed where a voltage on a wordline is changed from a first voltage to a second voltage via a plurality of intermediate voltages.

Claims

1. A method, comprising:

providing a memory arrangement comprising a plurality of wordlines;

changing a voltage of a selected wordline of the plurality of wordlines from a first voltage at which the wordline is deactivated to a second voltage at which the wordline is activated via a plurality of different intermediate voltages, each intermediate voltage being held for a respective certain time,

wherein a first difference in voltage between the first voltage and a first intermediate voltage, a second difference in voltage between adjacent intermediate voltages, and a third difference in voltage between a last intermediate voltage and the second voltage, are equal; and

accessing a memory cell coupled to the selected wordline only after the voltage has reached the second value.

2. The method of claim 1, wherein the certain time for each intermediate voltage is predetermined.

3. The method of claim 1, wherein the certain time for each intermediate voltage is determined depending on at least one of supply voltage, a process variation or temperature.

4. The method of claim 1, wherein the first voltage is a first supply voltage, and the second voltage is a second, different supply voltage.

5. The method of claim 1, further comprising changing the voltage on the wordline from the second voltage to a third voltage, the second voltage being between the first voltage and the third voltage, after the second voltage has been reached.

6. The method of claim 1, further comprising changing a voltage on a bitline after the wordline has reached the second voltage.

7. The method of claim 1, further comprising deactivating a first bitline precharging of at least one bitline coupled to a selected memory cell of the memory arrangement prior to the changing.

8. The method of claim 7 further comprising activating a second bitline precharging of the at least one bitline coupled to the selected memory, the second bitline precharging using smaller transistors than the first bitline precharging.

9. A device, comprising:

a memory arrangement, and

a wordline activation circuit configured to change a voltage on a selected wordline of the memory arrangement from a first voltage at which the wordline is deactivated to a second, different voltage at which the wordline is activated via a plurality of different intermediate voltages, each of the plurality of different intermediate voltages being held for a respective certain time,

wherein the device is configured to access a memory cell coupled to the selected wordline only after the voltage has reached the second value, and

wherein a first difference in voltage between the first voltage and a first intermediate voltage, a second difference in voltage between adjacent intermediate voltages, and a third difference in voltage between a last intermediate voltage and the second voltage, are equal.

10. The device of claim 9, wherein a number of the intermediate voltages is between 2 and 8.

11. The device of claim 9, wherein the certain time for each of the intermediate voltages is predetermined.

12. The device of claim 9, wherein the wordline activation circuit comprises a voltage divider.

13. The device of claim 9, further comprising

a weak bitline precharge device and a strong bitline precharge device each associated with bitlines of the memory arrangement, the weak bitline precharge device comprising smaller transistors than the strong bitline precharge device.

14. A device, comprising:

a transistor of a first conductivity type to be coupled between a first supply voltage and a wordline,

a plurality of transistors of a second, different conductivity type selectively coupled between the wordline and a second, different supply voltage, the plurality of transistors of the second conductivity type being selectively individually and independently activatable to adjust a wordline voltage to a plurality of different intermediate voltage values on the wordline.

15. The device of claim 14, further comprising a plurality of inverters, an input of each of the inverters being configured to receive a respective activation signal, an output of each of the inverters being coupled with one of the transistors of the second conductivity type, and a power supply of each of the inverters being coupled to the wordline.

16. The device of claim 14, wherein the transistor of the first conductivity type is selectively coupled to the first supply voltage or a third voltage, the first supply voltage having a value between the third voltage and the second supply voltage.

17. The device of claim 14, further comprising a further transistor of the second conductivity type coupled between the wordline and the second supply voltage, an activation input being coupled to the transistor of the first conductivity type and the further transistor of the second conductivity type.

18. A method, comprising:

providing a memory arrangement comprising a plurality of wordlines;

changing a voltage of a selected wordline of the plurality of wordlines from a first voltage at which the wordline is deactivated to a second voltage at which the wordline is activated via a plurality of different intermediate voltages, each intermediate voltage being held for a respective certain time;

accessing a memory cell coupled to the selected wordline only after the voltage has reached the second value; and

maintaining a charge of a first bitline of a bitline pair coupled to a selected memory cell of the memory arrangement by negative feedback of a voltage on a second bitline of said bitline pair.

19. A device, comprising:

a memory arrangement; and

a wordline activation circuit configured to change a voltage on a selected wordline of the memory arrangement from a first voltage at which the wordline is deactivated to a second, different voltage at which the wordline is activated via a plurality of different intermediate voltages, each of the plurality of different intermediate voltages being held for a respective certain time,

wherein the device is configured to access a memory cell coupled to the selected wordline only after the voltage has reached the second value, and

wherein the wordline activation circuit is further configured to apply an overdrive voltage having a value greater than the second voltage to the selected wordline after the second voltage has been reached.